ADVANCE PROGRAM

Tuesday April 16, 2002


13.00-19.00:Registration
19.00-21.00:Welcome Party (with buffet)


Wednesday April 17, 2002
08.30-09.00:Opening Session
B. Straube, General Chair DDECS'02
E.J. Marinissen, Program Chair DDECS'02
Z. Kotasek, Local Arrangements Chair DDECS'02

09.00-10.00:Invited Keynote, Sesion Chair: E.J. Marinissen - Philips Research, The Netherlands
B. Koenemann (IBM Microelectronics, San Jose, CA, USA): 2002: A Test Odyssey?
10.00 - 10.30:Poster Session 1: SOC Design and Simulation (+ Coffee Break), Session Chair: K. Vlcek - Technical University of Ostrava, Czech Republic
P1.1: V. Dvorak, V. Kutalek - Brno University of Technology, Czech Republic: Simulation and Prototyping Multiprocessor SOC with Hybrid Pipeline/Farm Architecture
P1.2: D. Navarro, G. Cathebras, G. Cambon - LIRMM, France: On The Implementation Of Census Transform In A CMOS Vision Chip
P1.3: T. Kangas, V. Lahtinen, K. Kuusilinna, T. Hamalainen - Tampere University of Technology, Finland: System-on-Chip Communication Optimization with Bus Monitoring
P1.4: J. Vanne, E. Aho, K. Kuusilinna, T. Hamalainen - Tampere University of Technology, Finland: Co-Simulation of Configurable Parallel Memory Architecture And Processor
P1.5: E.A.C. da Costa, S. Bampi, J.C. Monteiro - Instituto Superior Tecnico / INESC-ID, Portugal: FIR Filter Design using Low Power Arithmetic Operators
10.30-12.10:Paper Session 1: Digital Test and Testability, Session Chair: R. Ubar - Tallinn Technical University, Estonia
1.1: Z. Pliva, O. Novak, P. Bourdeu d'Aguerre - TU Liberec, Czech Republic: Hardware Overhead of Boundary Scan and RAS Design Methodologies
1.2: J. Strnadel, Z. Kotasek - Brno University of Technology, Czech Republic: Optimising Solution of the Scan Problem at RT Level Based on a Genetic Algorithm
1.3: E.J. Marinissen, S.K. Goel - Philips Research, The Netherlands: Analysis of Test Bandwidth Utilization in Test Bus and TestRail Architectures for SOCs
1.4: C.P. Su, C.W. Wu - National Tsing Hua University, Taiwan: Graph-Based Power-Constrained Test Scheduling for SOC
12.10-13.30:Lunch
13.30-14.45:Paper Session 2: Formal Methods in System Design, Session Chair: M. Balakrishnan - IIT Delhi, India
2.1: A. Darvas, I. Majzik, B. Benyo - Budapest University of Technology and Economics, Hungary: Verification of UML Statechart Models of Embedded Systems
2.2: R. Ruzicka - Brno University of Technology, Czech Republic: The Formal Approach to the RTL Test Application Problem Using Petri Nets
2.3: J. Schwarz, J. Ocenasek - Brno University of Technology, Czech Republic: Ratio-Cut Hypergraph Partitioning Using BDD Based MBOA Optimization Algorithm
15.00-19.00:Social Event: Visit to Austerlitz
19.30-21.30:Dinner in hotel


Thursday April 18, 2002
08.30-09.30:Invited Keynote Address, Session Chair: B. Straube - Fraunhofer Institute, Germany
R. Hartenstein (University of Kaiserlauterns, Germany): Configware / Software Co-Design: Be Prepared For the Next Revolution!
09.30-10.00:Poster Session 2: Formal Methods (+ Coffee Break), Session Chair: F. Novak - Josef Stefan Institute Ljublana, Slovenia
P2.1: M. Sveda - Brno University of Technology, Czech Republic: Rapid Prototyping of Embedded Distributed Systems
P2.2: P. Fiser, J. Hlavicka - Czech Technology University, Czech Republic: A Set of Logic Design Benchmarks
P2.3: M. Kollar - Technology University of Kosice, Slovakia: Using of the Flip-Flop Sensor in the Sigma-Delta Modulator for Measurement of the Thermal Characteristics of the Capacitors
P2.4: H. Kubatova - Czech Technology University, Czech Republic: How to Obtain Better Implementation of FSM in FPGA
P2.5: B. Steinbach, A. Zakrevskij - Freiburg University, Germany: New Approaches to Several Problem about ESOPs
P2.6: N. Fristacky, J. Kacerik - Slovak University of Technology, Slovakia: A Method of Formal Description of Digital System Inter-Module Communications and its Application
10.00-11.15:Paper Session 3: New Trends in ASIC/FPGA Design, Session Chair: R. Hartenstein - University of Kaiserslautern, Germany
3.1: A. Steininger, B. Rahbaran, M. Delvai, W. Huber- Vienna University of Technology, Austria: An FPGA-Based Development Platform for the Virtual Real-Time Processor Component SPEAR
3.2: M. Danek - Czech Technology University, Czech Republic: Reaching Optimal Performance of Timing-Driven Design Algorithms for FPGAs
3.3: T. Henriksson, N. Persson, D. Liu - Linkoping University, Sweden: VLSI Implementation of Internet Checksum Calculation for 10 Gigabit Ethernet
11.15-11.45:Poster Session 3: Testability Issues (+ Coffee Break), Session Chair: O. Novak - TU Liberec, Czech Republic
P3.1: A. Rashid Mohamed, Z. Peng, P. Eles - Linkoping University, Sweden: BIST Synthesis: An Approach to Resource Optimization under Test-Time Constraints
P3.2: M. Balaz, T. Pikula, P. Trebaticky, E. Gramatova - Slovak Academy of Sciences, SLovakia: Data Encryption Algorithm with Memory Self-Testing
P3.3: M. Lavasani, Z. Navabi Shirazi - University of Teheran, Iran: Intelligent Critical Path Selection for Ordered Test Pattern Generation
P3.4: V.N. Yarmolik, A.A. Ivaniuk - Belarussian State University of Informatics and Radioelectronics, Belarus: Built-In Self-Test and Diagnosis for RAM Based on Self-Adjusting Output Data Compression
11.45-12.35:Paper Session 4: Bio-Inspired Hardware, Session Chair: D. Badura - Silesian University in Katowice, Poland
4.1: A. Patzer - Duke University, USA: Highly Parallel DNA Sequence Matching and Alignment Processor
4.2: L. Sekanina, V. Drabek - Brno University of Technology, Czech Republic: Automatic Design of Image Operators Using Evolvable Hardware
12.35-14.00:Lunch
14.00-15.15:Paper Session 5: Hardware-Software Co-design, Session Chair: A. Pataricza - Budapest University of Technology and Econ., Hungary
5.1: M. Stork - University of West Bohemia, Czech Republic: Standard Median and Recursive Median Filters
5.2: Schmidt, Novotny, Jager, Becvar, Jachim - Czech Technology University, Czech Republic: Comparison of the Polynomial and Optimal Normal Basis ECDSA for GF(2^162)
5.3: P. Kukkala, T. Kangas, M. Hannikainen, T. Hamalainen - Tampere University of Technology, Finland: SDL Generated Protocols in Seamless Co-Verification Environment
15.15-15.45:Poster Session 4: Analogue and Defect Oriented Testing (+ Coffee Break), Session Chair: M. Renovell - LIRMM, France
P4.1: M. Luisa Gambina, G. Tuttobene - ST Microelectronics, Italy: WCDMA RF LNA-Mixer Testing
P4.2: M. Andrle, J. Holub, J. Vedral a R. Smid - Czech Technical University, Czech Republic: High Resolution ADC Testing by Means of Standard Test Methods
P4.3: M.B. Santos, I.M. Teixeira, J.P. Teixeira - INESC-ID / IST, Portugal: Dynamic Fault Injection Optimization for FPGA-Based Hardware Fault Simulation
P4.4: B. Polg r, E. Sel‚nyi - Budapest University of Technology and Econ., Hungary: Extensibility and Efficiency of Process-Graph Based Syndrome Decoding
15.45-17.00:Paper Session 6: Advances in Test Research, Session Chair: A. Hlawiczka - Silesian University of Technology, Poland
6.1: M. Renovell, J.M. Galliere, F. Azais, Y. Bertrand - LIRMM, France: Low Voltage Testing of Gate Oxide Short in CMOS Technology
6.2: F. Grasso, A. Luchetta, S. Manetti, M. C. Piccirilli - University of Florence, Italy: Automatic Generation of the Optimum Set of Frequencies for the Multifrequency Fault Diagnosis of Analog Circuits/ Symbolic Techniques in Parametric Fault Diagnosis
6.3: K. Elshafey, J. Hlavicka - Czech Technology University, Czech Republic: On-Line Detection and Location of Faulty CLBs in FPGA-Based Systems
17.00-17.30:Poster Session 5: HW-SW Codesign and IP Design (+ Coffee Break), Session Chair: Z. Kotasek - Brno University of Technology, Czech Republic
P5.1: S. Ben Saoud, D.D. Gajski - LECAP-EPT/INSAT, Tunisia: Seamless approach for the design of control systems for Power Electronics and Electric Drives
P5.2: Y. Le Moullec, J.P. Diguet, P. Koch - University de Bretagne Sud, France: A Power Aware System-Level Design Space Exploration Framework
P5.3: I. Mezei, M. Nikolic - University of Novi Sad, Yugoslavia: FPGA Based Hardware Emulation Used for Hardware/Software Functional Verification
P5.4: M. Witczynski, A. Pawlak - Silesian University of Technology, Poland: A New Paradigm of Engineering Work Enabled by Internet-Based Virtual Organisations
P5.5: S.Cerny, P. Struzka, D. Kolar - UNIS, Czech Republic: Source Code Generation by Reusable Component Oriented Encapsulation of Embedded System SW and HW
P5.6: T. Saari, M. Hannikainen, T. Hamalainen - Tampere University of Technology, Finland: Hardware Acceleration of Wireless LAN MAC Functions
20.00-23.00:Workshop Banquet


Friday April 19, 2002
08.30-10.10:Paper Session 7: Novel Architectures for SOC, Session Chair: V. Dvorak - Brno University of Technology, Czech Republic
7.1: U. Nordqvist, T. Henriksson, D. Liu - Linkopings University, Sweden: Configurable CRC Generator
7.2: T. Henriksson, I. Verbauwhede - Linkoping University, Sweden: Fast IP Address Lookup Engine for SoC Integration
7.3: E. Aho, J. Vanne, K. Kuusilinna, T. Hamalainen - Tampere University of Technology, Finland: Diamond Scheme Implementations in Configurable Parallel Memory
7.4: K. Khalilian, S. Ahmad - Infineon, Germany: Embedded Processor Cores: Design and Architectural Considerations for SoC Integration
10.10-10.40:Poster Session 6: Online Testing, Test Quality and Economics (+ Coffee Break), Session Chair: J. Hlavicka - Czech Technology University, Czech Republic
P6.1: V.V. Saposhnikov, A. Morozov, Vl.V. Saposhnikov, M. Goessel - University of Potsdam, Germany: Concurrent Checking By Use of Complementary Citrcuit for 1-out-of-3 Codes
P6.2: F. Rodriguez, J.C. Campelo, J.J. Serrano - University Politecnica de Valencia, Spain: A Distributed Simulation Environment for Fault Injection Analysis on SOC Models
P6.3: S. Blanc Clavero, A. Ademaj, H. Sivencrona - Chalmers University of Technology, Sweden: Achieving Improved Fault Detection Efficiency Combing Three Different Fault Injectors in Time-Triggered Systems
P6.4: O. Goloubeva, M. Sonza Reorda, M. Violante - Politecnico di Torina, Italy: Experimental Analysis of Fault Models for Behavioral-Level Test Generation
P6.5: A. Kristof - Silesian University of Technology, Poland: Interconnections Fault Models of Commercially Available Digital Electronic Components
10.40-12.20:Paper Session 8: Modeling and Simulation for SOC, Session Chair: Paolo Prinetto - Politecnico di Torino, Italy
8.1: A. B. Abril Garcia, J. Gobert, T. Dombek, H. Mehrez, F. Petrot - Philips Research, France: Energy Estimations in High Level Cycle-Accurate Descriptions of Embedded Systems
8.2: A.A. Moneim, K. Sharaf, H. Ragaie, M. Ibrahim - Ain Shams University in CAIRO, Egypt: Design of a 950-MHz CMOS Integrated Image Reject Front-End Receiver
8.3: E. Fomina, A. Keevallik, A. Sudnitson - Tallin Technical University, Estonia: Entropic Analysis of Finite State Machines' Networks
8.4: A. Oliveira, V. Sklyarov, A. Ferrari - University de Aveiro, Portugal: EaSys - A C++ Based Language for Digital Systems Design
12.20-13.30:Lunch
13.30-15.10:Paper Session 9: Test Generation / IP Based Design, Session Chair: S. Hellebrand - University of Innsbruck, Austria
9.1: S. Bawa, G.K. Sharma - IITM Gwalior, India: An Efficient Quadratic 0-1 Programming Algorithm for VLSI Test Generation
9.2: I.Skliarova, A.B. Ferrari - University de Aveiro, Portugal: A hardware/software approach to accelerate Boolean satisfiability
9.3: K. Venkatramani, L.H. Cooke - Cadence Design Systems, USA: Dealing with Asynchronous Design in an Synchronous IP World
9.4: M. Marrero, P.P. Carballo, G. Marrero, A. Nunez - Universidad de Las Palmas de Grand Canaria, Spain: A Design and Reuse Methodology for IP Soft-Cores with Built-in Performance Metrics
15.10:End of Workshop