Keynote speakers

Prof. Rolf Drechsler (University of Bremen/DFKI, Germany)
Hardware-Software Co-Visualization - Developing Systems in the Holodeck

Modern systems consisting of hardware and software are becoming more and more complex. The underlying data of next generation systems will consist of billions of entries in terms of components or lines of code. Handling this data efficiently is one of the major challenges for future EDA. In order to provide a meaningful preparation for these complex issues it is inevitable to deal with highly elaborated visualization techniques. It is unimaginable how data sets of this size could be grasped without advanced plotting methods. Although lots of effort has been put into research for visualization of software and hardware, they have been barely investigated in combination. Besides that, in most cases visualization techniques concentrate on the illustration of the system's structure and behavior, e.g. to ease debugging. However, far more information can be integrated. As an example, in the context of verification the accentuation of coverage metrics on top of the structural visualization of a system would immediately pinpoint the verification engineer to areas that are poorly validated. Furthermore, when considering the co- design of hardware-software systems, design exploration can be carried out much easier when the designer gets immediate visual feedback. Inspired by recent achievements in visualization methods and the invention of sophisticated machinery, in this paper we propose the use of Hardware-Software Co-Visualization (HSCV). The potential of current techniques as well as their limitations will be demonstrated. Furthermore, we are seeking for alternative methods in system visualization that go beyond monitors and printed pages. Techniques from 3D rendering and virtual reality are utilized for this purpose leading to a holistic environment in which complex systems can be grasped within seconds just as huge data sets in the context of plots. State-of-the-art is presented and directions for future work are outlined.

Erik Jan Marinissen (Principal Scientist at IMEC, Belgium)
Creating Options for 3D-SIC Testing

Three-dimensional stacked ICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all of the above can only become true if 3D-SICs can be properly tested for manufacturing defects. Companies have started to develop their test strategies for these products, and the outcome is largely dependent on (1) the necessity of test generation for specific new 3D defects, (2) the feasibility of access the test targets, and (3) the economic trade-offs involved. Test research is needed to create options for these challenges.

Prof. Kaushik Roy (Purdue University, USA)
Approximate Computing for Energy-efficient Error-resilient Multimedia Systems

In today's world there is an explosive growth in digital information content. Moreover, there is also a rapid increase in the number of users of multimedia applications related to image and video processing, recognition, mining and synthesis. These facts pose an interesting design challenge to process digital data in an energy-efficient manner while catering to desired user quality requirements. Most of these multimedia applications possess an inherent quality of "error"-resilience. This means that there is considerable room for allowing approximations in intermediate computations, as long as the final output meets the user quality requirements. This relaxation in "accuracy" can be used to simplify the complexity of computations at different levels of design abstraction, which directly helps in reducing the power consumption. At the algorithm and architecture levels, the computations can be divided into significant and non-significant. Significant computations have a greater impact on the overall output quality, compared to non-significant ones. Thus the underlying architecture can be modified to promote faster computation of significant components, thereby enabling voltage-scaling (at the same operating frequency). At the logic and circuit levels, one can relax Boolean equivalence to reduce the number of transistors and decrease the overall switched capacitance. This can be done in a controlled manner to introduce limited approximations in common mathematical operations like addition and multiplication. All these techniques can be classified under the general topic of "Approximate Computing", which is the main focus of this talk.