Events

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2010

Vienna 14.-16.4.2010

The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems provides a forum for exchanging ideas, discussing research results and presenting practical applications in the areas of design, test and diagnosis of microelectronic circuits and systems.

Programme Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT, chairman
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Steering Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT

Section moderators (members from FIT)

Růžička Richard, doc. Ing., Ph.D., MBA, UPSY FIT VUT, Student papers

Selected publications

2010FIŠER Petr, SCHMIDT Jan, VAŠÍČEK Zdeněk and SEKANINA Lukáš. On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 346-351. ISBN 978-1-4244-6610-8.
 KAŠTIL Jan and KOŘENEK Jan. Hardware Accelerated Pattern Matching Based on Deterministic Finite Automata with Perfect Hashing. In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Vienna: IEEE Computer Society, 2010, pp. 149-152. ISBN 978-1-4244-6610-8.
 KOTÁSEK Zdeněk, ŠKARVADA Jaroslav and STRNADEL Josef. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 364-369. ISBN 978-1-4244-6610-8.
 KOŘENEK Jan and KOŠAŘ Vlastimil. Efficient Mapping of Nondeterministic Automata to FPGA for Fast Regular Expression Matching. In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Vienna: IEEE Computer Society, 2010, p. 6. ISBN 978-1-4244-6610-8.
 KOŘENEK Jan and PUŠ Viktor. Memory Optimization for Packet Classification Algorithms in FPGA. In: Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vídeň: IEEE Computer Society, 2010, pp. 297-300. ISBN 978-1-4244-6610-8.
 SEKANINA Lukáš. Evolutionary Circuit Design: Tutorial. In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 5-5. ISBN 978-1-4244-6610-8.
 STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. In: Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010, pp. 173-176. ISBN 978-1-4244-6610-8.
 ŠIMEK Václav, RŮŽIČKA Richard and SEKANINA Lukáš. On Analysis of Fabricated Polymorphic Circuits. In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010, pp. 281-284. ISBN 978-1-4244-6610-8.

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