Events

Design, Automation and Test in Europe 2017

Lausanne 27.-30.3.2017

Programme Committee (members from FIT)

Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Section moderators (members from FIT)

Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT, Stochastic, approximate and neural computing

Selected publications

2017MRÁZEK Vojtěch, HRBÁČEK Radek, VAŠÍČEK Zdeněk and SEKANINA Lukáš. EvoApprox8b: Library of Approximate Adders and Multipliers for Circuit Design and Benchmarking of Approximation Methods. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 258-261. ISBN 978-3-9815370-9-3.
 VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Towards Low Power Approximate DCT Architecture for HEVC Standard. In: Proc. of the 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). Lausanne: European Design and Automation Association, 2017, pp. 1576-1581. ISBN 978-3-9815370-9-3.

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