Events

20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2017

Hotel Taschenbergpalais Kempinski, Dresden 19.-21.4.2017

Programme Committee (members from FIT)

Růžička Richard, doc. Ing., Ph.D., MBA, UPSY FIT VUT
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT
Zachariášová Marcela, Ing., Ph.D., UPSY FIT VUT

Steering Committee (members from FIT)

Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Section moderators (members from FIT)

Zachariášová Marcela, Ing., Ph.D., UPSY FIT VUT

Participants

Vašíček Zdeněk, doc. Ing., Ph.D., UPSY FIT VUT
Zachariášová Marcela, Ing., Ph.D., UPSY FIT VUT

Selected publications

2017VAŠÍČEK Zdeněk. Relaxed equivalence checking: a new challenge in logic synthesis. In: Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden: IEEE Computer Society, 2017, pp. 1-6. ISBN 978-1-5386-0472-4.

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