Events

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011

Cottbus 13.-15.4.2011

Programme Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Steering Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT, chairman

Selected publications

2011BARTOŠ Pavel, KOTÁSEK Zdeněk and DOHNAL Jan. Decreasing Test Time by Scan Chain Reorganization. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 371-374. ISBN 978-1-4244-9753-9.
 KOŠAŘ Vlastimil and KOŘENEK Jan. Reduction of FPGA Resources for Regular Expression Matching by Relation Similarity. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 401-402. ISBN 978-1-4244-9753-9.
 MATOUŠEK Jiří and KORČEK Pavol. Precise IPv4/IPv6 Packet Generator Based on NetCOPE Platform. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 319-324. ISBN 978-1-4244-9756-0.
 PUŠ Viktor, KAJAN Michal and KOŘENEK Jan. Hardware Architecture for Packet Classification with Prefix Coloring. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 231-236. ISBN 978-1-4244-9753-9.
 PŘIKRYL Zdeněk, KŘOUSTEK Jakub, HRUŠKA Tomáš and KOLÁŘ Dušan. Fast Just-In-Time Translated Simulator for ASIP Design. In: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011, pp. 279-282. ISBN 978-1-4244-9753-9.
 RŮŽIČKA Richard, ŠIMEK Václav and SEKANINA Lukáš. Behavior of CMOS Polymorphic Circuits in High Temperature Environment. In: Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Cottbus: IEEE Computer Society, 2011, pp. 447-452. ISBN 978-1-4244-9753-9.
 STRAKA Martin, KAŠTIL Jan, NOVOTNÝ Jaroslav and KOTÁSEK Zdeněk. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 397-398. ISBN 978-1-4244-9753-9.
 TOBOLA Jiří and KOŘENEK Jan. Effective Hash-based IPv6 Longest Prefix Match. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011, pp. 325-328. ISBN 978-1-4244-9753-9.

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