Events

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013

Karlovy Vary 8.-10.4.2013

The IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of electronic circuits and systems.

Organizing Committee (members from FIT)

Růžička Richard, doc. Ing., Ph.D., MBA, UPSY FIT VUT, chairman
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT
Šimek Václav, Ing., UPSY FIT VUT
Vašíček Zdeněk, doc. Ing., Ph.D., UPSY FIT VUT

Programme Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT
Růžička Richard, doc. Ing., Ph.D., MBA, UPSY FIT VUT
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Steering Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT, chairman

Section moderators (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT
Růžička Richard, doc. Ing., Ph.D., MBA, UPSY FIT VUT
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Selected publications

2013KADLČEK Filip and FUČÍK Otto. Automatic synthesis of small AdaBoost Classifier in FPGA. In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2013. Brno: IEEE Computer Society, 2013, pp. 1-6. ISBN 978-1-4673-6133-0.
 KAŠTIL Jan, KOŠAŘ Vlastimil and KOŘENEK Jan. Hardware Architecture for the Fast Pattern Matching. In: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Brno: IEEE Computer Society, 2013, pp. 120-123. ISBN 978-1-4673-6133-0.
 KOŘENEK Jan. Hardware Acceleration of Algorithms in Computer Networks using FPGA. In: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Brno: IEEE Computer Society, 2013, pp. 11-11. ISBN 978-1-4673-6133-0.
 MATOUŠEK Jiří, SKAČAN Martin and KOŘENEK Jan. Towards Hardware Architecture for Memory Efficient IPv4/IPv6 Lookup in 100 Gbps Networks. In: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Brno: IEEE Computer Society, 2013, pp. 108-111. ISBN 978-1-4673-6136-1.
 PETRLÍK Jiří and SEKANINA Lukáš. Multiobjective evolution of approximate multiple constant multipliers. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Brno: IEEE Computer Society, 2013, pp. 116-119. ISBN 978-1-4673-6133-0.
 SEKANINA Lukáš, FEY Görschwin, RAIK Jaan, AUNET Snorre and RŮŽIČKA Richard, ed. IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Brno: IEEE Computer Society, 2013. ISBN 978-1-4673-6133-0.
 STRNADEL Josef. On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems. In: Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Brno: IEEE Computer Society, 2013, pp. 24-29. ISBN 978-1-4673-6133-0.
 SZURMAN Karel, KAŠTIL Jan, STRAKA Martin and KOTÁSEK Zdeněk. Fault Tolerant CAN Bus Control System Implemented into FPGA. In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013. Karlovy Vary: IEEE Computer Society, 2013, pp. 289-292. ISBN 978-1-4673-1185-4.
 ZACHARIÁŠOVÁ Marcela, BOLCHINI Cristiana and KOTÁSEK Zdeněk. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. In: IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013, pp. 275-278. ISBN 978-1-4673-6133-0.

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