Events

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2014

Warsaw 23.-25.4.2014

Programme Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT
Růžička Richard, doc. Ing., Ph.D., MBA, UPSY FIT VUT
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Steering Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT, chairman
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Section moderators (members from FIT)

Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Selected publications

2014DVOŘÁK Milan and KOŘENEK Jan. Low Latency Book Handling in FPGA for High Frequency Trading. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 175-178. ISBN 978-1-4799-4558-0.
 KEKELY Lukáš, ŽÁDNÍK Martin, MATOUŠEK Jiří and KOŘENEK Jan. Fast Lookup for Dynamic Packet Filtering in FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 219-222. ISBN 978-1-4799-4558-0.
 KOTÁSEK Zdeněk and MIČULKA Lukáš. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 171-174. ISBN 978-0-7695-5074-9.
 KOŠAŘ Vlastimil and KOŘENEK Jan. On NFA-Split Architecture Optimizations. In: 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Warsaw: IEEE Computer Society, 2014, pp. 274-277. ISBN 978-1-4799-4558-0.
 PLESKACZ Witold, RENOVELL Michel, SEKANINA Lukáš, BERNARD Serge and KASPROWICZ Dominik, ed. IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Warsaw: IEEE Computer Society, 2014. ISBN 978-1-4799-4560-3.
 PUŠ Viktor, KEKELY Lukáš and KOŘENEK Jan. Design Methodology of Configurable High Performance Packet Parser for FPGA. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 189-194. ISBN 978-1-4799-4558-0.
 VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evolutionary Design of Approximate Multipliers Under Different Error Metrics. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warsaw: IEEE Computer Society, 2014, pp. 135-140. ISBN 978-1-4799-4558-0.
 ZÁVODNÍK Tomáš, KEKELY Lukáš and PUŠ Viktor. CRC based hashing in FPGA using DSP blocks. In: 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014, pp. 179-182. ISBN 978-1-4799-4558-0.

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