Events

IEEE Design and Diagnostics of Electronic Circuits and Systems 2002

Brno 17.-19.4.2002

DDECS Workshop is an event organized by Central European countries; the 5th DDECS 2002 is organized by the Faculty of Information Technology of the Brno University of Technology in Czech Republic and sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC). Four previous workshops were held in Czech Republic (1997), Poland (1998), Slovakia (2000) and Hungary (2001). The 6th DDECS 2003 Workshop will take place in Poland. The DDECS Workshop has been conceived as a forum for presenting and discussing trends and hot topics in the area of electronic circuit and system design and diagnostics. These two areas are obviously closely related and covering them jointly brings a big potential for mutual stimulation. The Workshop is intended to give researchers, in particular young investigators coming from both academia and industry, a chance to present their results and discuss trends and needs in the areas related to design and diagnostics. This would have a very positive effect both on the academic life and industrial development in Central and Eastern Europe.

Organizing Committee (members from FIT)

Čejka Rudolf, Ing., CVT FIT VUT
Linhart Miroslav, doc. Ing., CSc., UPSY FIT VUT
Růžička Richard, doc. Ing., Ph.D., MBA, UPSY FIT VUT, chairman
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT
Strnadel Josef, Ing., Ph.D., UPSY FIT VUT

Programme Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT

Steering Committee (members from FIT)

Hlavička Jan, Prof. Ing., DrSc., FEL ČVUT
Hrynkiewicz Edward, Instytut elektroniki Politechniki Śląskiej
Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT
Novák Ondřej, Ing., FIT VUT
Straube Bernd, Dr. Ing. habil., Fraunhofer Institut fuer Integrierte Schaltungen

Section moderators (members from FIT)

Drábek Vladimír, doc. Ing., CSc., UPSY FIT VUT, Online Testing, Test Quality and Economics
Drábek Vladimír, doc. Ing., CSc., UPSY FIT VUT
Drábek Vladimír, doc. Ing., CSc., UPSY FIT VUT
Dvořák Václav, prof. Ing., DrSc., UPSY FIT VUT, Novel Architectures for SoC
Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT, HW-SW Codesign and IP Design

Selected publications

2002HLAVIČKA Jan, KOTÁSEK Zdeněk, MARINISSEN Erik Jan, NOVÁK Ondřej, RŮŽIČKA Richard and STRAUBE Bernd, ed. Proceedings of 5th International Workshop IEEE Design and Diagnostics of Electronic Circuits and Systems. Brno: Faculty of Information Technology BUT, 2002. ISBN 80-214-2094-4.
 KUTÁLEK Vladimír and DVOŘÁK Václav. Simulation and Prototyping Multiprocessor SoC with Hybrid Pipeline/Farm Architecture. In: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and System Workshop. Brno: Faculty of Information Technology BUT, 2002, pp. 296-299. ISBN 80-214-2094-4.
 RŮŽIČKA Richard. The Formal Approach to the RTL Test Application Problem Using Petri Nets. In: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems 2002. Brno: Faculty of Information Technology BUT, 2002, pp. 78-86. ISBN 80-214-2094-4.
 SCHWARZ Josef and OČENÁŠEK Jiří. Ratio cut hypergraph partitioning using BDD based MBOA optimization algorithm. In: Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Brno: Faculty of Informatics and Information Technology Slovak University of Technology in Bratislava, 2002, pp. 87-96. ISBN 80-214-2094-4.
 SEKANINA Lukáš and DRÁBEK Vladimír. Automatic Design of Image Operators Using Evolvable Hardware. In: Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Brno: Brno University of Technology, 2002, pp. 132-139. ISBN 80-214-2094-4.
 STRNADEL Josef and KOTÁSEK Zdeněk. Optimising Solution of the Scan Problem at RT Level Based on a Genetic Algorithm. In: Proceedings of 5th IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop. Brno: Brno University of Technology, 2002, pp. 44-51. ISBN 80-214-2094-4.
 ŠVÉDA Miroslav. Rapid Prototyping of Embedded Distributed Systems. In: IEEE Design and Diagnostics of Electronic Circuits and Systems. Brno: Faculty of Information Technology BUT, 2002, pp. 320-323. ISBN 80-214-2094-4.
 ČERNÝ Stanislav, KOLÁŘ Dušan and STRUŽKA Petr. Processor Expert, Component Application Builder for Embedded Systems. In: Proceedings of 5th IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop. Brno: Faculty of Information Technology BUT, 2002, pp. 393-397. ISBN 80-214-2094-4.
2000SCHWARZ Josef and OČENÁŠEK Jiří. The knowledge-based evolutionary algorithm KBOA for hypergraph bisectioning. In: Proceedings of the Fourth Joint Conference on Knowledge-Based Software Engineering Brno, Czech Republic, 2000. BRNO: IOS Press, 2000, pp. 51-58. ISBN 1-58603-060-4.

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