Events

The 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

Sopron 13.-16.4.2005

The IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) is intended to provide a forum for exchanging ideas, and presenting research results and practical applications in the areas of design, test and diagnostics of microelectronic circuits and systems.

Programme Committee (members from FIT)

Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Steering Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT

Speakers

Bryan Luděk, Ing., UPSY FIT VUT
Jaroš Jiří, doc. Ing., Ph.D., UPSY FIT VUT
Kořenek Jan, Ing., Ph.D., UPSY FIT VUT
Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT
Martínek Tomáš, Ing., Ph.D., UPSY FIT VUT
Pečenka Tomáš, Ing., UPSY FIT VUT
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT
Strnadel Josef, Ing., Ph.D., UPSY FIT VUT

Selected publications

2005BRYAN Luděk, FUČÍK Otto and ŠUSTEK Jiří. Environment for Hw/Sw Codesign of Embedded Systems. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, pp. 236-240. ISBN 9639364487.
 JAROŠ Jiří and DVOŘÁK Václav. Speeding-up OAS and AAS Communication in Networking System on Chips. In: Proc. of 8th IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Sopron: University of West Hungary, 2005, p. 4. ISBN 9639364487.
 KOTÁSEK Zdeněk, STRNADEL Josef and PEČENKA Tomáš. Methodology of Selecting Scan-Based Testability Improving Technique. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, pp. 186-189. ISBN 963-9364-48-7.
 MARTÍNEK Tomáš, ZEMČÍK Pavel and KOŘENEK Jan. FPGA-Based Platform for Network Applications. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, pp. 194-197. ISBN 963-9364-48-7.
 PEČENKA Tomáš. At-speed testování spojů na kartě COMBO6. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, pp. 221-223. ISBN 963-9364-48-7.
 SEKANINA Lukáš. Design Methods for Polymorphic Digital Circuits. In: Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, pp. 145-150. ISBN 9639364487.
 STRNADEL Josef. VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements. In: Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005, pp. 190-193. ISBN 963-9364-48-7.

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