Events

IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop

Praha 18.-21.4.2006

Programme Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT

Steering Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT

Section moderators (members from FIT)

Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT, Student Session I.
Schwarz Josef, doc. Ing., CSc., UPSY FIT VUT, Physical and IP Design

Speakers

Gajda Zbyšek, Ing., Ph.D., UPSY FIT VUT
Jaroš Jiří, Ing., Ph.D., UPSY FIT VUT
Kořenek Jan, Ing., Ph.D., UPSY FIT VUT
Kotásek Zdeněk, doc. Ing., CSc., UPSY FIT VUT
Martínek Tomáš, Ing., Ph.D., UPSY FIT VUT
Ohlídal Miloš, Ing., UPSY FIT VUT
Pečenka Tomáš, Ing., UPSY FIT VUT
Sekanina Lukáš, prof. Ing., Ph.D., UPSY FIT VUT
Schwarz Josef, doc. Ing., CSc., UPSY FIT VUT
Stareček Lukáš, Ing., UPSY FIT VUT
Strnadel Josef, Ing., Ph.D., UPSY FIT VUT
Škarvada Jaroslav, Ing., Ph.D., UPSY FIT VUT

Selected publications

2006GAJDA Zbyšek. A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 238-240. ISBN 1424401844.
 JAROŠ Jiří and DVOŘÁK Václav. Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 222-223. ISBN 1-4244-0184-4.
 MARTÍNEK Tomáš, LEXA Matej, KOŘENEK Jan and FUČÍK Otto. A flexible technique for the automatic design of approximate string matching architectures. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 83-84. ISBN 1-4244-0184-4.
 OHLÍDAL Miloš and SCHWARZ Josef. Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 224-225. ISBN 1-4244-0184-4.
 PEČENKA Tomáš, KOTÁSEK Zdeněk and SEKANINA Lukáš. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 285-289. ISBN 1424401844.
 SEKANINA Lukáš, STAREČEK Lukáš and KOTÁSEK Zdeněk. Novel Logic Circuits Controlled by Vdd. In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006, pp. 85-86. ISBN 1424401844.
 STRNADEL Josef. Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space. In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006, pp. 161-162. ISBN 1-4244-0184-4.
 ŠKARVADA Jaroslav. Test Scheduling for SOC under Power Constraints. In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006, pp. 91-93. ISBN 1-4244-0184-4.

Your IPv4 address: 54.157.81.13
Switch to IPv6 connection

DNSSEC [dnssec]