IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop

 

Praha 18.-21.4.2006

Programme Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc.
Sekanina Lukáš, prof. Ing., Ph.D.

Steering Committee (members from FIT)

Kotásek Zdeněk, doc. Ing., CSc.

Section moderators (members from FIT)

Sekanina Lukáš, prof. Ing., Ph.D., Student Session I.
Schwarz Josef, doc. Ing., CSc., Physical and IP Design

Speakers

Gajda Zbyšek, Ing., Ph.D.
Jaroš Jiří, Ing., Ph.D.
Kořenek Jan, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Martínek Tomáš, Ing., Ph.D.
Ohlídal Miloš, Ing.
Pečenka Tomáš, Ing.
Sekanina Lukáš, prof. Ing., Ph.D.
Schwarz Josef, doc. Ing., CSc.
Stareček Lukáš, Ing.
Strnadel Josef, Ing., Ph.D.
Škarvada Jaroslav, Ing., Ph.D.

Selected publications

2006Gajda Zbyšek: A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 238-240, ISBN 1424401844
 Jaroš Jiří, Dvořák Václav: Evolutionary Design of OAB and AAB Communication Schedules for Networking Systems on Chips, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 222-223, ISBN 1-4244-0184-4
 Martínek Tomáš, Lexa Matej, Kořenek Jan, Fučík Otto: A flexible technique for the automatic design of approximate string matching architectures, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 83-84, ISBN 1-4244-0184-4
 Ohlídal Miloš, Schwarz Josef: Collective Communication AAB for Regular and Irregular Topology Based on Prediction of Conflicts, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 224-225, ISBN 1-4244-0184-4
 Pečenka Tomáš, Kotásek Zdeněk, Sekanina Lukáš: FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 285-289, ISBN 1424401844
 Sekanina Lukáš, Stareček Lukáš, Kotásek Zdeněk: Novel Logic Circuits Controlled by Vdd, In: Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, Praha, CZ, IEEE CS, 2006, p. 85-86, ISBN 1424401844
 Strnadel Josef: Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space, In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Prague, CZ, VCVUT, 2006, p. 161-162, ISBN 1-4244-0184-4
 Škarvada Jaroslav: Test Scheduling for SOC under Power Constraints, In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Prague, CZ, VCVUT, 2006, p. 91-93, ISBN 1-4244-0184-4

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