Zvyšování spolehlivost a provozuschopnosti v obvodech SoC
Hlavní řešitel:Kotásek Zdeněk
Spoluřešitelé:Bartoš Pavel, Kaštil Jan, Mičulka Lukáš, Slimařík František, Straka Martin, Strnadel Josef
Agentura:GAČR
Kód:GA102/09/1668
Začátek:2009
Konec:2011
Klíčová slova:systémy odolné proti poruchám, spolehlivost
Anotace:
We propose a basic research project that is aimed at utilizing and deepening the current results of three research groups in the field of on-line and off-line testing and diagnostics with the intension to utilize them in the design of fault tolerant systems. The fault tolerant methodologies will be developed on three levels: level of error tolerance, level of single-event upset detection with additional reconfiguration and a level of system architecture graceful degradation in case of unrecoverable faults appearance. The goal of this project is to design a new, advanced design methodology for fault-tolerant circuits that will be based on the new technological possibilities.

Produkty

Publikace

2011Bartoš, P., Kotásek, Z., Dohnal, J.: Decreasing Test Time by Scan Chain Reorganization, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, s. 371-374, ISBN 978-1-4244-9753-9
 Bartoš, P.: Metody reorganizace řetězce scan, In: Počítačové architektury a diagnostika 2011, Bratislava, SK, Vyd. STU, 2011, s. 97-102, ISBN 978-80-227-3552-0
 Bartoš, P.: Test Time Reduction by Scan Chain Reordering, In: Proceedings of the 17th Conference STUDENT EEICT 2011, Brno, CZ, FEKT VUT, 2011, s. 564-568, ISBN 978-80-214-4273-3
 Mičulka, L.: Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA, In: Počítačové architektury & diagnostika 2011, Bratislava, SK, FIIT STU, 2011, s. 61-66, ISBN 978-80-227-3552-0
 Rumplík, M., Strnadel, J.: On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits, In: Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011, Oulu, FI, IEEE CS, 2011, s. 367-374, ISBN 978-0-7695-4494-6
 Růžička, R., Šimek, V.: Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles, In: Proceedings of 14th Euromicro Conference on Digital System Design, Los Alamitos, US, ICSP, 2011, s. 205-212, ISBN 978-0-7695-4494-6
 Straka, M., Kaštil, J., Kotásek, Z.: SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems, In: 14th EUROMICRO Conference on Digital System Design, Oulu, FI, IEEE CS, 2011, s. 223-230, ISBN 978-0-7695-4494-6
 Straka, M., Kaštil, J., Novotný, J., Kotásek, Z.: Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, s. 397-398, ISBN 978-1-4244-9753-9
 Strnadel, J.: Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads, In: Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design, Oulu, FI, JKUL, 2011, s. 21-22, ISBN 978-3-902457-30-1
 Strnadel, J.: Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems, In: Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium, Vienna, AT, TUV, 2011, s. 29-32
2010Bartoš, P.: Optimalizace propojení řetězce scan po ukončení fyzického návrhu, In: Počítačové architektury a diagnostika 2010, Brno, CZ, FIT VUT, 2010, s. 21-26, ISBN 978-80-214-4140-8
 Fišer, P., Schmidt, J., Vašíček, Z., Sekanina, L.: On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming, In: Proc. of the 13th Int. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, AT, IEEE CS, 2010, s. 346-351, ISBN 978-1-4244-6610-8
 Kotásek, Z., Škarvada, J., Strnadel, J.: Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences, In: Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, AT, IEEE CS, 2010, s. 364-369, ISBN 978-1-4244-6610-8
 Kotásek, Z., Škarvada, J., Strnadel, J.: The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption, In: Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools, Los Alamitos, US, IEEE CS, 2010, s. 644-651, ISBN 978-0-7695-4171-6
 Růžička, R.: Gracefully Degrading Circuit Controllers Based on Polytronics, In: Proc. of 13th Euromicro Conference on Digital System Design, Los Alamitos, US, IEEE CS, 2010, s. 809-812, ISBN 978-0-7695-4171-6
 Straka, M., Kaštil, J., Kotásek, Z.: Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration, In: 13th EUROMICRO Conference on Digital System Design, DSD'2010, Lille, FR, IEEE CS, 2010, s. 365-372, ISBN 978-0-7695-4171-6
 Straka, M., Kaštil, J., Kotásek, Z.: Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA, In: NORCHIP 2010, Tampere, FI, IEEE CS, 2010, s. 1-4, ISBN 978-1-4244-8971-8
 Straka, M., Kaštil, J., Kotásek, Z.: Methodology for Design of Highly Dependable Systems in FPGA, In: International Scientific Conference on Computer Science and Engineering, Košice, SK, TU v Košiciach, 2010, s. 186-193, ISBN 978-80-8086-164-3
 Straka, M., Kaštil, J., Kotásek, Z.: Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs, In: Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010, Wien, AT, IEEE CS, 2010, s. 173-176, ISBN 978-1-4244-6610-8
 Straka, M.: Metodika pro návrh číslicových systémů se zvýšenou spolehlivostí v obvodech FPGA, In: Počítačové architektury a diagnostika 2010, Brno, CZ, FIT VUT, 2010, s. 159-164, ISBN 978-80-214-4140-8
 Strnadel, J.: Návrh časově kritických systémů I: specifikace a verifikace, In: Automa, roč. 2010, č. 10, CZ, s. 42-44, ISSN 1210-9592
 Strnadel, J.: Task-Level Modeling and Design of Components for Construction of Dependable Time-Critical Systems Implemented by Means of RT Kernel, In: Sborník přednášek z 33. mezinárodní konference TD 2010 - DIAGON 2010, Zlín, CZ, UTB ve Zlíně, 2010, s. 99-104, ISBN 978-80-7318-940-2
 Škarvada, J., Kotásek, Z., Strnadel, J.: Optimalizace aplikace testu číslicových systémů pro nízký příkon, Brno, CZ, FIT VUT, 2010, s. 142, ISBN 978-80-214-4209-2
 Škarvada, J., Kotásek, Z., Strnadel, J.: The Use of Genetic Algorithm to Reduce Power Consumption during Test Application, In: Evolvable Systems: From Biology to Hardware, Berlin, DE, Springer, 2010, s. 181-192, ISBN 978-3-642-15322-8, ISSN 0302-9743
2009Kotásek, Z., Straka, M.: The Design of On-line Checkers and Their Use in Verification and Testing, In: Acta Electrotechnica et Informatica, roč. 2009, č. 3, SK, s. 8-15, ISSN 1335-8243
 Straka, M., Kotásek, Z.: High Availability Fault Tolerant Architectures Implemented into FPGAs, In: 12th EUROMICRO Conference on Digital System Design DSD 2009, Patras, GR, IEEE CS, 2009, s. 108-116, ISBN 978-0-7695-3782-5
 Straka, M.: Metodologie návrhu obvodů se zvýšenou spolehlivostí založených na FPGA, In: Počítačové architektury a diagnostika 2009, Zlin, CZ, UTB ve Zlíně, 2009, s. 141-146, ISBN 978-80-7318-847-4
 Strnadel, J.: Overview of Mechanisms for Improving Reliability of Embedded Real-Time Systems, In: Proceedings of 32th International Conference TD - DIAGON 2009, Zlín, CZ, UTB ve Zlíně, 2009, s. 19-24, ISBN 978-80-7318-840-5

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