Project Details

Metody návrhu aplikací založených na vyvíjejících se obvodech

Project Period: 1. 1. 2003 - 31. 12. 2005

Project Type: grant

Code: GP102/03/P004

Agency: Czech Science Foundation

Program:

English title
Evolvable hardware based applications design methods
Type
grant
Keywords

hardware; computational intelligence; evolvable hardware; design methodology

Abstract

The project deals with evolvable hardware, i.e. it combines evolutionary algorithms with reconfigurable hardware. Evolvable hardware enables to design high-performance and adaptive solutions for such applications in which the problem specification is unknown in the design time or can vary in time. The routine design of such applications is in fact impossible in Field Programmable Gate Arrays (FPGA) nowadays. The goal of the project is to introduce, develop, and test a methodology for evolvable hardware based application(s) design, which utilizes common FPGAs. In particular, a design system that will assist the designer during application design and which will enable to generate the description of application's software as well as hardware parts (e.g. as IP macros) will be developed. The methodology will be based on component approach to evolvable hardware and virtual reconfigurable devices introduced by the proposer. Adaptive embedded (e.g. multimedia) systems represent typical application domain of the project. A typical application will be designed using the proposed methodology.

Team members
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY FIT VUT) , research leader
Publications

2006

  • ZEBULUM Ricardo S., KEYMEULEN Didier, RAMESHAM Rajeshuni, SEKANINA Lukáš, MAO James, KUMAR Nikhil and STOICA Adrian. Characterization and Synthesis of Circuits at Extreme Low Temperatures. Evolvable Hardware. Genetic and Evolutionary Computation. Berlin: Springer Verlag, 2006, pp. 161-172. ISBN 0-387-24386-0. Detail

2005

  • MARTÍNEK Tomáš and SEKANINA Lukáš. An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, vol. 3637. Berlin: Springer Verlag, 2005, pp. 76-85. ISBN 978-3-540-28736-0. Detail
  • SEKANINA Lukáš. Evoluční design poráží řešení vytvořená kreativním návrhářem. Vesmír, vol. 84, no. 1, 2005, pp. 44-46. ISSN 0042-4544. Detail
  • SEKANINA Lukáš and BIDLO Michal. Evolutionary Design of Arbitrarily Large Sorting Networks Using Development. Genetic Programming and Evolvable Machines, vol. 6, no. 3, 2005, pp. 319-347. ISSN 1389-2576. Detail
  • SEKANINA Lukáš. Evolutionary Design of Gate-Level Polymorphic Digital Circuits. In: Applications of Evolutionary Computation. Lecture Notes in Computer Science, vol. 3449. Berlin: Springer Verlag, 2005, pp. 185-194. ISBN 978-3-540-25396-9. Detail
  • SEKANINA Lukáš and ZEBULUM Ricardo S. Evolutionary discovering of the concept of the discrete state at the transistor level. In: Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005, pp. 73-78. ISBN 0-7695-2399-4. Detail
  • ZEBULUM Ricardo S., STOICA Adrian, KEYMEULEN Didier and SEKANINA Lukáš. Evolvable Hardware System at Extreme Low Temperatures. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, vol. 3637. Berlin: Springer Verlag, 2005, pp. 37-45. ISBN 978-3-540-28736-0. Detail
  • KOŘENEK Jan and SEKANINA Lukáš. Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs. In: Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science, vol. 3637. Berlin: Springer Verlag, 2005, pp. 46-55. ISBN 978-3-540-28736-0. Detail
  • BIDLO Michal and SEKANINA Lukáš. Providing Information from the Environment for Growing Electronic Circuits Through Polymorphic Gates. In: Proc. of Genetic and Evolutionary Computation Conference - Workshops 2005. New York: Association for Computing Machinery, 2005, pp. 242-248. ISBN 1-59593-097-3. Detail

2004

  • SEKANINA Lukáš and FRIEDL Štěpán. An Evolvable Combinational Unit for FPGAs. Computing and Informatics, vol. 23, no. 5, 2004, pp. 461-486. ISSN 1335-9150. Detail
  • DRÁBEK Vladimír. Binární algebry a kódy aneb ten nádherný binární svět. In: I & IT'04 Informatika a informačné technológie 2004. Banská Bystrica: University of Matej Bel in Banska Bystrica, 2004, pp. 111-118. ISBN 80-8083-017-7. Detail
  • TORRESEN Jim, BAKKE Jorgen W. and SEKANINA Lukáš. Efficient Image Filtering and Information Reduction in Reconfigurable Logic. In: Proc. of 2004 Norchip conference. Oslo: IEEE Computer Society Press, 2004, pp. 63-66. ISBN 0-7803-8510-1. Detail
  • TORRESEN Jim, BAKKE Jorgen W. and SEKANINA Lukáš. Efficient Recognition of Speed Limit Signs. In: Proc. of the 7th International IEEE Conference on Intelligent Transportation Systems. Los Alamos: IEEE Computer Society Press, 2004, pp. 652-656. ISBN 0-7803-8501-2. Detail
  • VAŠÍČEK Zdeněk and SEKANINA Lukáš. Evoluční návrh kombinačních obvodů. Elektrorevue - www.elektrorevue.cz, vol. 2004, no. 43, pp. 1-6. ISSN 1213-1539. Detail
  • SEKANINA Lukáš. Evolutionary Design Space Exploration for Median Circuits. Lecture Notes in Computer Science, vol. 2004, no. 3005, pp. 240-249. ISSN 0302-9743. Detail
  • SEKANINA Lukáš. Evolvable computing by means of evolvable components. Natural Computing, vol. 3, no. 3, 2004, pp. 323-355. ISSN 15677818. Detail
  • SEKANINA Lukáš. Evolving Constructors for Infinitely Growing Sorting Networks and Medians. Lecture Notes in Computer Science, vol. 2004, no. 2932, pp. 314-323. ISSN 0302-9743. Detail
  • SEKANINA Lukáš and FRIEDL Štěpán. On Routine Implementation of Virtual Evolvable Devices Using COMBO6. In: Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2004, pp. 63-70. ISBN 0-7695-2145-2. Detail
  • TORRESEN Jim, BAKKE Jorgen W. and SEKANINA Lukáš. Recognizing Speed Limit Sign Numbers by Evolvable Hardware. Lecture Notes in Computer Science, vol. 2004, no. 3242, pp. 682-691. ISSN 0302-9743. Detail
  • FRIEDL Štěpán and SEKANINA Lukáš. The First Circuits Evolved in a Physical Virtual Reconfigurable Device. In: Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004, pp. 35-42. ISBN 80-969117-9-1. Detail
  • SEKANINA Lukáš and DRÁBEK Vladimír. Theory and Applications of Evolvable Embedded Systems. In: Proc. of the 11th IEEE Int. Conference and Workshop on the Engineering of Computer-Based Systems. Los Alamitos, CA: IEEE Computer Society Press, 2004, pp. 186-193. ISBN 0-7695-2125-8. Detail

2003

  • SEKANINA Lukáš and RŮŽIČKA Richard. Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. In: The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003, pp. 135-144. ISBN 0-7695-1977-6. Detail
  • SEKANINA Lukáš. Evolvable Components - From Theory to Hardware Implementations. Natural Computing Series. Berlin: Springer Verlag, 2003. ISBN 3-540-40377-9. Detail
  • SEKANINA Lukáš. From Implementations to a General Concept of Evolvable Machines. Lecture Notes in Computer Science, vol. 2003, no. 2610, pp. 424-433. ISSN 0302-9743. Detail
  • SEKANINA Lukáš. Towards Evolvable IP Cores for FPGAs. In: Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003, pp. 145-154. ISBN 0-7695-1977-6. Detail
  • SEKANINA Lukáš. Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. Lecture Notes in Computer Science, vol. 2003, no. 2606, pp. 186-197. ISSN 0302-9743. Detail
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