Project Details

Metodiky pro návrh systémů odolných proti poruchám do rekonfigurovatelných architektur - vývoj, implementace a verifikace

Project Period: 1. 3. 2012 - 30. 11. 2015

Project Type: grant

Code: LD12036

Agency: Ministry of Education, Youth and Sports Czech Republic

Program: COST CZ (2011-2017)

English title
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification
Type
grant
Keywords

digital circuit, checker, fault tolerant system, SEU, simulation, generator, testing, verification, FPGA, reconfiguration, controller,
methodology

Abstract

The project has these goals and steps of research:

1) Development and implementation of a new methodology for fault tolerant systems design into FPGA including error detection, faults localization, reconfiguration and synchronization after reconfiguration process.

2) Development and implementation of a new methodology for automated generation of diagnostic resources for on-line testing of FPGA based systems.

3) Development of techniques for the verification of fault tolerant systems quality together with SEU injector tool to be used for reconfigurable platforms.

4) Experimental evaluation of the methodology.

5) The analysis of project results.

Team members
Kotásek Zdeněk, doc. Ing., CSc. (UPSY FIT VUT) , research leader
Čekan Ondřej, Ing., Ph.D. (UPSY FIT VUT) , team leader
Kaštil Jan, Ing. (UPSY FIT VUT) , team leader
Mičulka Lukáš, Ing. (UPSY FIT VUT) , team leader
Podivínský Jakub, Ing., Ph.D. (UPSY FIT VUT) , team leader
Straka Martin, Ing., Ph.D. (UPSY FIT VUT) , team leader
Strnadel Josef, Ing., Ph.D. (UPSY FIT VUT) , team leader
Zachariášová Marcela, Ing., Ph.D. (UPSY FIT VUT) , team leader
Krčma Martin, Ing. (UPSY FIT VUT)
Szurman Karel, Ing., Ph.D. (UPSY FIT VUT)
Files
Publications

2015

2014

2013

2012

Products

2015

2012

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