Reduced Certification Costs Using Trusted Multi-core Platforms

Reseach leader:Zemčík Pavel
Team leaders:Smrž Pavel
Team members:Ševcovic Jiří
Agency:Artemis JU
Code:RECOMP
Start:2010
End:2013
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Keywords:multi-core platforms, certification
Annotation:
The RECOMP (Reduced certification cost for trusted multi-core platforms) research project will establish methods, tools and platforms for enabling cost-efficient certification and re-certification of safety-critical systems and mixed-criticality systems, i.e. systems containing safety-critical and nonsafety-
critical components.
RECOMP recognizes the fact that the increasing processing power of embedded systems is mainly provided by increasing the number of processing cores. The increased numbers of cores is commonly
regarded as a design challenge in the safety-critical area, as there are no established approaches to achieve certification.
At the same time there is an increased need for flexibility in the products in the safety-critical market.
This need for flexibility puts new requirements on the customization and the upgradability of both the non-safety and safety-critical critical part. The difficulty with this is the large cost in both effort and money of the re-certification of the modified software, which means that companies cannot fully leverage the advantages of modular software system.
RECOMP will provide reference designs and platform architectures together with the required design methods and tools for achieving cost-effective certification and re-certification of mixed-criticality,
component based, multi-core systems. The aim of RECOMP is to define a European standard reference technology for mixed-criticality multi-core systems supported by the European tool vendors participating in RECOMP.
The RECOMP project will bring clear benefits in terms of cross-domain implementations of mixed criticality systems in all domains addressed by project participants: automotive systems, aerospace
systems, industrial control systems, lifts and transportation systems.
RECOMP will thus provide solutions that will allow European industry to increase its market share in the growing market of mixed-criticality systems.

Products

2013intMAN: Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems, prototype, 2013
Authors: Strnadel Josef, Šimek Václav
2012HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware, software, 2012
Authors: Šimková Marcela, Lengál Ondřej, Kajan Michal
 Hybrid platform for prototyping of safety embedded systems, specimen, 2012
Authors: Šimek Václav, Růžička Richard

Publications

2013Strnadel, J.: Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates, In: Architecture of Computing Systems - ARCS 2013, Berlin, DE, Springer, 2013, p. 98-109, ISBN 978-3-642-36423-5
 Strnadel, J.: On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems, In: Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electrical Circuits and Systems, Brno, CZ, IEEE CS, 2013, p. 24-29, ISBN 978-1-4673-6136-1
2012Dittrich, P.: Identification of Flight Parameters of Light Sport Aircraft, In: Proceedings of the 18th Conference STUDENT EEICT 2012, Brno, CZ, VUT v Brně, 2012, p. 464-468, ISBN 978-80-214-4462-1
 Juránek, R., Hradiš, M., Zemčík, P.: Real-time Algorithms of Object Detection with Classifiers, Real-Time System, Rijeka, HR, InTech, 2012, p. 1-22, ISBN 9789535105107
 Kaštil, J., Straka, M., Kotásek, Z.: Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration, In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12), Annecy, FR, Polimi, 2012, p. 1-4
 Kaštil, J., Straka, M., Mičulka, L., Kotásek, Z.: Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA, In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Cesme-Izmir, TR, IEEE CS, 2012, p. 250-257, ISBN 978-0-7695-4798-5
 Mičulka, L., Kotásek, Z.: Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System, In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Cesme-Izmir, TR, IEEE CS, 2012, p. 20-21, ISBN 978-3-902457-33-2
 Straka, M., Kaštil, J., Kotásek, Z., Mičulka, L.: Fault Tolerant System Design and SEU Injection based Testing, In: Microprocessors and Microsystems, Vol. 2013, No. 37, 2012, Amsterdam, NL, p. 155-173, ISSN 0141-9331
 Straka, M., Kaštil, J., Kotásek, Z.: Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems, In: CSE'2012 International Scientific Conference on Computer Science and Engineering, Košice, SK, TU v Košiciach, 2012, p. 146-153, ISBN 978-80-8143-049-7
 Straka, M., Mičulka, L., Kaštil, J., Kotásek, Z.: Test Platform for Fault Tolerant Systems Design Qualities Verification, In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Tallin, EE, IEEE CS, 2012, p. 336-341, ISBN 978-1-4673-1185-4
 Strnadel, J.: Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems, In: Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Tallin, EE, IEEE CS, 2012, p. 121-126, ISBN 978-1-4673-1188-5
 Šimková, M., Kaštil, J., Kotásek, Z.: Verification of Fault-tolerant methodologies for FPGA Systems, In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12), Annecy, FR, Polimi, 2012, p. 55-58
 Šimková, M., Lengál, O., Kajan, M.: HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware, In: Lecture Notes in Computer Science, Vol. 2012, No. 7261, DE, p. 247-253, ISSN 0302-9743
2011Dittrich, P., Chudý, P.: Application of Kalman Filter to oversampled data from Global Position System, In: ElectroScope, Vol. 2011, No. 2, Plzeň, CZ, p. 6, ISSN 1802-4564
 Strnadel, J.: Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads, In: Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design, Oulu, FI, JKUL, 2011, p. 21-22, ISBN 978-3-902457-30-1
 Strnadel, J.: Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems, In: Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium, Vienna, AT, TUV, 2011, p. 29-32
 Šimková, M., Lengál, O., Kajan, M.: HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware, FIT-TR-2011-05, Brno, CZ, FIT VUT, 2011, p. 16
 Zemčík, P., Maršík, L., Široký, V., Fučík, O., Korček, P., Šustek, J.: AX32 Low Power Embedded Video Enabled System Using FPGA, In: Proceedings of the 21th Conference on Field Programmable Logic and Applications Workshop, Chania, GR, IEEE, 2011, p. 2, ISBN 978-0-7695-4529-5

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