Fault Tolerant Systems Design, Diagnostics and Testing
- Scope: The research group is primarily engaged in dependability of electronic systems with special attention paid to the area of fault tolerance and its verification.
- Publication activities: Among other things, group members publish their papers at international conferences such as IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) or Euromicro Conference on Digital System Design (DSD) and in journals such as Microprocessors and Microsystems or Computing and Informatics.
- Offer: We welcome cooperation and offer the opportunity to engage others in our research topics (e.g., during the PhD study or intership).
- Fault tolerant systems (on-line testing techniques, checkers, dependability models, partial dynamic reconfiguration based on an FPGA, overload prevention solutions for embedded systems).
- The use of functional verification outputs for the verification of fault tolerance properties of electromechanical systems, the use of fault injection.
- The design of fault tolerant neural networks, the verification of fault tolerance parameters.
Current research themes
- Increasing dependability by means of partial dynamic reconfiguration in an FPGA (contact: Zdeněk Kotásek). Keywords: partial dynamic reconfiguration, control, controller, FPGA.
- Means of a fault injection into an FPGA (contact: Zdeněk Kotásek). Keywords: fault, injection, FPGA.
- Methods for acceleration of functional verification (contact: Marcela Šimková). Keywords: functional verification, acceleration, automation.
- Dependability of embedded critical systems driven by an operating system (contact: Josef Strnadel). Keywords: adaptation, COTS, MCU, task, operating system, OS, real time, RTOS, control, scheduler, monitoring, interrupt management.
- For realization purposes, we use particularly field programmable gate arrays (FPGA) and development tools from Xilinx, microcontrollers (MCU) and development tools from Freescale and tools from Mentor Graphics.
Brno University of Technology
Faculty of Information Technology
Department of Computer Systems
612 66 Brno