Diagnostics Research Group
Publications| 2013 | Strnadel Josef: Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates, In: Architecture of Computing Systems - ARCS 2013, Berlin, DE, Springer, 2013, p. 98-109, ISBN 978-3-642-36423-5 |
| | Strnadel Josef: On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems, In: Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electrical Circuits and Systems, Brno, CZ, IEEE CS, 2013, p. 24-29, ISBN 978-1-4673-6136-1 |
| | Szurman Karel, Kaštil Jan, Straka Martin, Kotásek Zdeněk: Fault Tolerant CAN Bus Control System Implemented into FPGA, In: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2013, Karlovy Vary, CZ, IEEE CS, 2013, p. 289-292, ISBN 978-1-4673-1185-4 |
| | Šimková Marcela, Bolchini Cristiana, Kotásek Zdeněk: Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability, In: IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Karlovy Vary, CZ, IEEE CS, 2013, p. 275-278, ISBN 978-1-4673-6133-0 |
| | Šimková Marcela, Přikryl Zdeněk, Hruška Tomáš, Kotásek Zdeněk: Automated Functional Verification of Application Specific Instruction-set Processors, In: The IESS 2013 Proceedings, Heidelberg, DE, Springer, 2013, p. 1-10 |
| 2012 | Kaštil Jan, Straka Martin, Kotásek Zdeněk: Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration, In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12), Annecy, FR, Polimi, 2012, p. 1-4 |
| | Kaštil Jan, Straka Martin, Mičulka Lukáš, Kotásek Zdeněk: Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA, In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Cesme-Izmir, TR, IEEE CS, 2012, p. 250-257, ISBN 978-0-7695-4798-5 |
| | Kotásek Zdeněk, Škarvada Jaroslav: Low Power Testing, Design and Test Technology foír Dependable Systems-on-Chip, Hershey, US, IGI Global, 2012, p. 395-412, ISBN 978-1-60960-212-3 |
| | Mičulka Lukáš, Kotásek Zdeněk: Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System, In: 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Cesme-Izmir, TR, IEEE CS, 2012, p. 20-21, ISBN 978-3-902457-33-2 |
| | Mičulka Lukáš: Metoda návrh systémů odolných proti poruchám do omezeného implementačního prostoru na bázi FPGA, In: Počítačové architektury & diagnostika 2012, Praha, CZ, FIT ČVUT, 2012, p. 109-115, ISBN 978-80-01-05106-1 |
| | Straka Martin, Kaštil Jan, Kotásek Zdeněk, Mičulka Lukáš: Fault Tolerant System Design and SEU Injection based Testing, In: Microprocessors and Microsystems, Vol. 2013, No. 37, 2012, Amsterdam, NL, p. 155-173, ISSN 0141-9331 |
| | Straka Martin, Kaštil Jan, Kotásek Zdeněk: FPGA-based Fault Tolerant Architectures and Their Dependability Analysis, In: MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, FI MUNI, 2012, p. 1-1 |
| | Straka Martin, Kaštil Jan, Kotásek Zdeněk: Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems, In: CSE'2012 International Scientific Conference on Computer Science and Engineering, Košice, SK, TU v Košiciach, 2012, p. 146-153, ISBN 978-80-8143-049-7 |
| | Straka Martin, Mičulka Lukáš, Kaštil Jan, Kotásek Zdeněk: Test Platform for Fault Tolerant Systems Design Qualities Verification, In: 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Tallin, EE, IEEE CS, 2012, p. 336-341, ISBN 978-1-4673-1185-4 |
| | Strnadel Josef, Rajnoha Peter: Reflecting RTOS Model During WCET Timing Analysis: MSP430/FreeRTOS Case Study, In: Acta Electrotechnica et Informatica, Vol. 12, No. 4, 2012, SK, p. 17-29, ISSN 1335-8243 |
| | Strnadel Josef, Slimařík František: On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels, In: Proceedings of the 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, Pistacaway, US, IEEE CS, 2012, p. 272-279, ISBN 978-0-7695-4798-5 |
| | Strnadel Josef: Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems, In: Proceedings of the 15th International IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Tallin, EE, IEEE CS, 2012, p. 121-126, ISBN 978-1-4673-1188-5 |
| | Šimková Marcela, Lengál Ondřej: Towards Beneficial Hardware Acceleration in HAVEN: Evaluation of Testbed Architectures, FIT-TR-2012-03, Brno, CZ, FIT VUT, 2012, p. 14 |
| | Šimková Marcela: Acceleration of Functional Verification in the Development Cycle of Hardware Systems, In: Počítačové architektury a diagnostika, Praha, CZ, ČVUT, 2012, p. 73-78, ISBN 978-80-01-05106-1 |
| 2011 | Bartoš Pavel, Kotásek Zdeněk, Dohnal Jan: Decreasing Test Time by Scan Chain Reorganization, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, p. 371-374, ISBN 978-1-4244-9753-9 |
| | Bartoš Pavel: Metody optimalizace propojení scan řetězce, In: Počítačové architektury a diagnostika 2011, Bratislava, SK, Vyd. STU, 2011, p. 97-102, ISBN 978-80-227-3552-0 |
| | Bartoš Pavel: Test Time Reduction by Scan Chain Reordering, In: Proceedings of the 17th Conference STUDENT EEICT 2011, Brno, CZ, FEKT VUT, 2011, p. 564-568, ISBN 978-80-214-4273-3 |
| | Herrman Tomáš: Metodika aplikace testu obvodu založená na identifikaci testovatelných bloků, Brno, CZ, 2011, p. 95 |
| | Rumplík Michal, Strnadel Josef: On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits, In: Proceedings of the 14th Euromicro Conference on Digital System Design - Architectures, Methods and Tools 2011, Oulu, FI, IEEE CS, 2011, p. 367-374, ISBN 978-0-7695-4494-6 |
| | Straka Martin, Kaštil Jan, Kotásek Zdeněk: SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems, In: 14th EUROMICRO Conference on Digital System Design, Oulu, FI, IEEE CS, 2011, p. 223-230, ISBN 978-0-7695-4494-6 |
| | Straka Martin, Kaštil Jan, Novotný Jaroslav, Kotásek Zdeněk: Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, p. 397-398, ISBN 978-1-4244-9753-9 |
| | Strnadel Josef: Concept of Adaptive Embedded HW/SW Architecture for Dynamic Prevention from Interrupt Overloads, In: Proceedings of the Work in Progress Session held in connection with SEAA 2011, the 37th EUROMICRO Conference on Software Engineering and Advanced Applications and DSD 2011, the 14th EUROMICRO Conference on Digital System Design, Oulu, FI, JKUL, 2011, p. 21-22, ISBN 978-3-902457-30-1 |
| | Strnadel Josef: Návrh časově kritických systémů III: priorita úloh, In: Automa, Vol. 2011, No. 2, CZ, p. 50-52, ISSN 1210-9592 |
| | Strnadel Josef: Návrh časově kritických systémů IV: realizace prostředky RTOS, In: Automa, Vol. 2011, No. 4, CZ, p. 58-60, ISSN 1210-9592 |
| | Strnadel Josef: Proposal of Flexible Monitoring-Driven HW/SW Interrupt Management for Embedded COTS-Based Event-Triggered Real-Time Systems, In: Proceedings of the Work-in-Progress Session of the 32nd IEEE Real-Time Systems Symposium, Vienna, AT, TUV, 2011, p. 29-32 |
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Faculty of Information Technology
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