Fault Tolerant Systems Design, Diagnostics and Testing

Team members

Drábek Vladimír, doc. Ing., CSc., member, UPSY FIT VUT
  • diagnosis of digital systems
  • fault-tolerant and fail-safe systems
  • design automation with VHDL
  • algorithms of arithmetic calculations
  • applications of finite-field algebra
  • compression and processing of multimedia data
  • graphical and multimedia processors
Kaštil Jan, Ing., member, UPSY FIT VUT
  • Návrh systémů do FPGA
Kotásek Zdeněk, doc. Ing., CSc., Principal researcher, UPSY FIT VUT
  • Digital circuit diagnostics and testing
  • Digital circuit testability analysis
  • Design and synthesis for testability
  • Fault-tolerant systems design methodologies
Krčma Martin, Ing., member, UPSY FIT VUT
 
Lojda Jakub, Ing., member, UPSY FIT VUT
 
Mičulka Lukáš, Ing., member, UPSY FIT VUT
 
Pánek Richard, Ing., member, UPSY FIT VUT
 
Podivínský Jakub, Ing., member, UPSY FIT VUT
 
Strnadel Josef, Ing., Ph.D., member, UPSY FIT VUT
  • Modeling, analysis and design of dynamic systems
  • Dependability and fault tolerance; digital circuit design, diagnosis, digital circuit testability analysis at register-transfer level
  • Critical, embedded and cyber-physical systems
  • Real-time (operating) systems
Zachariášová Marcela, Ing., Ph.D., member, UPSY FIT VUT
  • Functional verification (SystemVerilog, OVM).
  • Hardware accelerated functional verification using FPGA technology.
  • Coverage driven verification using genetic programming and machine-learning algorithms. 
  • Design and testing of fault-tolerant systems.
  • Automated generation of verification environments.

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