// Library = EvoApprox 12x12 // Circuit = mul12x12_226 // Area (45) = 118 // Delay (45) = 0.520 // Power (45) = 0.04 // MAE = 416755.70000 // MSE = 254306487625.50000 // MRE = 300.97 % // WCE = 1597866 // WCRE = 65536300 % // EP = 100.0 % module mul12x12_226(A, B, O); input [11:0] A, B; output [23:0] O; wire n_1365, n_1364, n_1750, n_44, n_47, n_46, n_41, n_40, n_1756, n_42; wire n_1594, n_1284, n_1819, n_1818, n_1446, n_30, n_31, n_32, n_33, n_34; wire n_35, n_36, n_37, n_38, n_39, n_1742, n_45, n_1290, n_1952, n_1438; wire n_23, n_22, n_21, n_20, n_27, n_26, n_25, n_24, n_29, n_28; wire n_1736, n_1972, n_1973, n_2021, n_2020, n_2026, n_18, n_19, n_16, n_17; wire n_14, n_15, n_12, n_13, n_10, n_11, n_94, n_98, n_99, n_1602; wire n_1967, n_1966, n_1521, n_1520, n_1668, n_1669, n_2034, n_2040, n_43, n_1981; wire n_1980, n_211, n_210, n_1134, n_1824, n_1825, n_1677, n_1676, n_63, n_62; wire n_61, n_60, n_1831, n_1830, n_8, n_9, n_4, n_5, n_6, n_7; wire n_0, n_1, n_2, n_3, n_1926, n_1884, n_58, n_1588; assign n_0 = A[0]; assign n_1 = A[0]; assign n_2 = A[1]; assign n_3 = A[1]; assign n_4 = A[2]; assign n_5 = A[2]; assign n_6 = A[3]; assign n_7 = A[3]; assign n_8 = A[4]; assign n_9 = A[4]; assign n_10 = A[5]; assign n_11 = A[5]; assign n_12 = A[6]; assign n_13 = A[6]; assign n_14 = A[7]; assign n_15 = A[7]; assign n_16 = A[8]; assign n_17 = A[8]; assign n_18 = A[9]; assign n_19 = A[9]; assign n_20 = A[10]; assign n_21 = A[10]; assign n_22 = A[11]; assign n_23 = A[11]; assign n_24 = B[0]; assign n_25 = B[0]; assign n_26 = B[1]; assign n_27 = B[1]; assign n_28 = B[2]; assign n_29 = B[2]; assign n_30 = B[3]; assign n_31 = B[3]; assign n_32 = B[4]; assign n_33 = B[4]; assign n_34 = B[5]; assign n_35 = B[5]; assign n_36 = B[6]; assign n_37 = B[6]; assign n_38 = B[7]; assign n_39 = B[7]; assign n_40 = B[8]; assign n_41 = B[8]; assign n_42 = B[9]; assign n_43 = B[9]; assign n_44 = B[10]; assign n_45 = B[10]; assign n_46 = B[11]; assign n_47 = B[11]; assign n_58 = ~(n_38 | n_16 | n_42); assign n_60 = n_42 & n_58; assign n_61 = n_60; assign n_62 = ~n_61; assign n_63 = n_62; assign n_94 = ~n_61; assign n_98 = ~n_61; assign n_99 = n_98; assign n_210 = ~n_63; assign n_211 = n_210; assign n_1134 = n_22 & n_38; assign n_1284 = n_20 & n_40; assign n_1290 = n_211; assign n_1364 = n_1134 & n_1284; assign n_1365 = n_1364; assign n_1438 = n_20 & n_42; assign n_1446 = n_22 & n_42; FAX1 tmp76(.YS(n_1520), .YC(n_1521), .A(n_1290), .B(n_1438), .C(n_1365)); assign n_1588 = n_18 & n_44; assign n_1594 = n_20 & n_44; assign n_1602 = n_22 & n_44; assign n_1668 = n_1520 | n_1588; assign n_1669 = n_1668; FAX1 tmp82(.YS(n_1676), .YC(n_1677), .A(n_1446), .B(n_1594), .C(n_1521)); assign n_1736 = n_16 & n_46; assign n_1742 = n_18 & n_46; assign n_1750 = n_20 & n_46; assign n_1756 = n_22 & n_46; HAX1 tmp87(.YS(n_1818), .YC(n_1819), .A(n_63), .B(n_1736)); FAX1 tmp88(.YS(n_1824), .YC(n_1825), .A(n_1676), .B(n_1742), .C(n_1669)); FAX1 tmp89(.YS(n_1830), .YC(n_1831), .A(n_1602), .B(n_1750), .C(n_1677)); assign n_1884 = n_61; assign n_1926 = n_1818 | n_40; assign n_1952 = n_1884 | n_1926; HAX1 tmp93(.YS(n_1966), .YC(n_1967), .A(n_1824), .B(n_1819)); FAX1 tmp94(.YS(n_1972), .YC(n_1973), .A(n_1830), .B(n_1825), .C(n_1967)); FAX1 tmp95(.YS(n_1980), .YC(n_1981), .A(n_1756), .B(n_1831), .C(n_1973)); assign n_2020 = n_1966; assign n_2021 = n_2020; assign n_2026 = n_1972; assign n_2034 = n_1980; assign n_2040 = n_1981; assign O[0] = n_18; assign O[1] = n_28; assign O[2] = n_99; assign O[3] = n_16; assign O[4] = n_26; assign O[5] = n_1290; assign O[6] = n_46; assign O[7] = n_8; assign O[8] = n_34; assign O[9] = n_12; assign O[10] = n_22; assign O[11] = n_32; assign O[12] = n_26; assign O[13] = n_4; assign O[14] = n_46; assign O[15] = n_40; assign O[16] = n_18; assign O[17] = n_94; assign O[18] = n_22; assign O[19] = n_1952; assign O[20] = n_2021; assign O[21] = n_2026; assign O[22] = n_2034; assign O[23] = n_2040; endmodule