// Library = EvoApprox 12x12 // Circuit = mul12x12_234 // Area (45) = 126 // Delay (45) = 0.610 // Power (45) = 0.04 // MAE = 407420.70000 // MSE = 255253738051.50000 // MRE = 164.87 % // WCE = 1635086 // WCRE = 26214700 % // EP = 100.0 % module mul12x12_234(A, B, O); input [11:0] A, B; output [23:0] O; wire n_1947, n_1946, n_949, n_948, n_45, n_1953, n_47, n_46, n_41, n_40; wire n_43, n_42, n_2018, n_2019, n_146, n_2010, n_2011, n_1626, n_1627, n_30; wire n_31, n_32, n_33, n_34, n_35, n_36, n_37, n_38, n_39, n_1952; wire n_44, n_1866, n_1692, n_23, n_22, n_21, n_20, n_27, n_26, n_25; wire n_24, n_29, n_28, n_1874, n_2027, n_2026, n_18, n_19, n_16, n_17; wire n_1961, n_1960, n_12, n_13, n_10, n_11, n_1714, n_14, n_81, n_80; wire n_15, n_1858, n_1548, n_1540, n_2041, n_2040, n_1794, n_1795, n_2032, n_2033; wire n_1706, n_65, n_64, n_1380, n_1787, n_1786, n_8, n_9, n_4, n_5; wire n_6, n_7, n_0, n_1, n_2, n_3, n_1880, n_56; assign n_0 = A[0]; assign n_1 = A[0]; assign n_2 = A[1]; assign n_3 = A[1]; assign n_4 = A[2]; assign n_5 = A[2]; assign n_6 = A[3]; assign n_7 = A[3]; assign n_8 = A[4]; assign n_9 = A[4]; assign n_10 = A[5]; assign n_11 = A[5]; assign n_12 = A[6]; assign n_13 = A[6]; assign n_14 = A[7]; assign n_15 = A[7]; assign n_16 = A[8]; assign n_17 = A[8]; assign n_18 = A[9]; assign n_19 = A[9]; assign n_20 = A[10]; assign n_21 = A[10]; assign n_22 = A[11]; assign n_23 = A[11]; assign n_24 = B[0]; assign n_25 = B[0]; assign n_26 = B[1]; assign n_27 = B[1]; assign n_28 = B[2]; assign n_29 = B[2]; assign n_30 = B[3]; assign n_31 = B[3]; assign n_32 = B[4]; assign n_33 = B[4]; assign n_34 = B[5]; assign n_35 = B[5]; assign n_36 = B[6]; assign n_37 = B[6]; assign n_38 = B[7]; assign n_39 = B[7]; assign n_40 = B[8]; assign n_41 = B[8]; assign n_42 = B[9]; assign n_43 = B[9]; assign n_44 = B[10]; assign n_45 = B[10]; assign n_46 = B[11]; assign n_47 = B[11]; assign n_56 = ~(n_34 & n_44 & n_38); assign n_64 = ~(n_44 | n_56); assign n_65 = n_64; assign n_80 = ~n_65; assign n_81 = n_80; assign n_146 = ~n_81; assign n_948 = ~n_81; assign n_949 = n_948; assign n_1380 = n_22 & n_40; assign n_1540 = n_20 & n_42; assign n_1548 = n_22 & n_42; FAX1 tmp70(.YS(n_1626), .YC(n_1627), .A(n_1380), .B(n_1540), .C(n_22)); assign n_1692 = n_16 & n_146; assign n_1706 = n_20 & n_44; assign n_1714 = n_22 & n_44; assign n_1786 = n_1626 & n_44; assign n_1787 = n_1786; FAX1 tmp76(.YS(n_1794), .YC(n_1795), .A(n_1548), .B(n_1706), .C(n_1627)); assign n_1858 = n_16 & n_46; assign n_1866 = n_18 & n_46; assign n_1874 = n_20 & n_46; assign n_1880 = n_22 & n_46; HAX1 tmp81(.YS(n_1946), .YC(n_1947), .A(n_18), .B(n_1858)); FAX1 tmp82(.YS(n_1952), .YC(n_1953), .A(n_1794), .B(n_1866), .C(n_1787)); FAX1 tmp83(.YS(n_1960), .YC(n_1961), .A(n_1714), .B(n_1874), .C(n_1795)); assign n_2010 = ~n_949; assign n_2011 = n_2010; HAX1 tmp86(.YS(n_2018), .YC(n_2019), .A(n_1946), .B(n_1692)); FAX1 tmp87(.YS(n_2026), .YC(n_2027), .A(n_1952), .B(n_1947), .C(n_2019)); FAX1 tmp88(.YS(n_2032), .YC(n_2033), .A(n_1960), .B(n_1953), .C(n_2027)); FAX1 tmp89(.YS(n_2040), .YC(n_2041), .A(n_1880), .B(n_1961), .C(n_2033)); assign O[0] = n_34; assign O[1] = n_44; assign O[2] = n_2011; assign O[3] = n_64; assign O[4] = n_10; assign O[5] = n_4; assign O[6] = n_46; assign O[7] = n_8; assign O[8] = n_65; assign O[9] = n_28; assign O[10] = n_6; assign O[11] = n_32; assign O[12] = n_26; assign O[13] = n_36; assign O[14] = n_14; assign O[15] = n_40; assign O[16] = n_18; assign O[17] = n_12; assign O[18] = n_2010; assign O[19] = n_2018; assign O[20] = n_2026; assign O[21] = n_2032; assign O[22] = n_2040; assign O[23] = n_2041; endmodule