// Library = EvoApprox 12x12 // Circuit = mul12x12_270 // Area (45) = 45 // Delay (45) = 0.260 // Power (45) = 0.01 // MAE = 907832.70000 // MSE = 1209191130683.50000 // MRE = 529.80 % // WCE = 3326674 // WCRE = 108547200 % // EP = 100.0 % module mul12x12_270(A, B, O); input [11:0] A, B; output [23:0] O; wire n_704, n_45, n_44, n_47, n_1115, n_41, n_40, n_43, n_42, n_49; wire n_48, n_1118, n_1280, n_1281, n_2014, n_1444, n_30, n_31, n_32, n_33; wire n_34, n_35, n_36, n_37, n_38, n_39, n_2009, n_2008, n_1297, n_1296; wire n_2003, n_2002, n_1114, n_46, n_1450, n_1457, n_1456, n_23, n_22, n_21; wire n_20, n_27, n_26, n_25, n_24, n_29, n_28, n_832, n_838, n_2021; wire n_2020, n_18, n_19, n_16, n_17, n_14, n_1124, n_12, n_13, n_10; wire n_11, n_826, n_2024, n_1125, n_81, n_80, n_15, n_103, n_102, n_1660; wire n_770, n_1666, n_2036, n_2030, n_2031, n_1673, n_1672, n_60, n_1462, n_1463; wire n_8, n_9, n_4, n_5, n_6, n_7, n_0, n_1, n_2, n_3; wire n_58, n_52, n_53, n_56, n_57, n_54, n_55, n_766; assign n_0 = A[0]; assign n_1 = A[0]; assign n_2 = A[1]; assign n_3 = A[1]; assign n_4 = A[2]; assign n_5 = A[2]; assign n_6 = A[3]; assign n_7 = A[3]; assign n_8 = A[4]; assign n_9 = A[4]; assign n_10 = A[5]; assign n_11 = A[5]; assign n_12 = A[6]; assign n_13 = A[6]; assign n_14 = A[7]; assign n_15 = A[7]; assign n_16 = A[8]; assign n_17 = A[8]; assign n_18 = A[9]; assign n_19 = A[9]; assign n_20 = A[10]; assign n_21 = A[10]; assign n_22 = A[11]; assign n_23 = A[11]; assign n_24 = B[0]; assign n_25 = B[0]; assign n_26 = B[1]; assign n_27 = B[1]; assign n_28 = B[2]; assign n_29 = B[2]; assign n_30 = B[3]; assign n_31 = B[3]; assign n_32 = B[4]; assign n_33 = B[4]; assign n_34 = B[5]; assign n_35 = B[5]; assign n_36 = B[6]; assign n_37 = B[6]; assign n_38 = B[7]; assign n_39 = B[7]; assign n_40 = B[8]; assign n_41 = B[8]; assign n_42 = B[9]; assign n_43 = B[9]; assign n_44 = B[10]; assign n_45 = B[10]; assign n_46 = B[11]; assign n_47 = B[11]; assign n_48 = ~(n_28 & n_14 & n_38); assign n_49 = n_48; assign n_52 = ~(n_49 | n_28); assign n_53 = n_52; assign n_54 = ~(n_34 | n_28 | n_38); assign n_55 = n_54; assign n_56 = ~(n_34 & n_55); assign n_57 = n_56; assign n_58 = ~n_53; assign n_60 = ~n_57; assign n_80 = ~n_57; assign n_81 = n_80; assign n_102 = ~n_57; assign n_103 = n_102; assign n_704 = n_22 & n_42; assign n_766 = n_20 & n_44; assign n_770 = n_22 & n_44; assign n_826 = n_18 & n_46; assign n_832 = n_20 & n_46; assign n_838 = n_22 & n_46; FAX1 tmp79(.YS(n_1114), .YC(n_1115), .A(n_704), .B(n_766), .C(n_826)); assign n_1118 = n_770 & n_832; HAX1 tmp81(.YS(n_1124), .YC(n_1125), .A(n_770), .B(n_832)); assign n_1280 = ~n_57; assign n_1281 = n_1280; assign n_1296 = ~n_81; assign n_1297 = n_1296; assign n_1444 = n_1124 & n_1115; assign n_1450 = n_1124 | n_1115; assign n_1456 = n_1297 & n_1118; assign n_1457 = n_1456; HAX1 tmp90(.YS(n_1462), .YC(n_1463), .A(n_838), .B(n_1118)); assign n_1660 = n_1450; assign n_1666 = n_1462 & n_1444; HAX1 tmp93(.YS(n_1672), .YC(n_1673), .A(n_1462), .B(n_1444)); FAX1 tmp94(.YS(n_2002), .YC(n_2003), .A(n_1660), .B(n_52), .C(n_1457)); FAX1 tmp95(.YS(n_2008), .YC(n_2009), .A(n_1672), .B(n_102), .C(n_2003)); assign n_2014 = n_1456 | n_1666; assign n_2020 = ~n_2009; assign n_2021 = n_2020; assign n_2024 = n_1281 | n_2002; MUX2X1 tmp100(.Y(n_2030), .A(n_38), .B(n_2008), .S(n_2021)); assign n_2031 = n_2030; assign n_2036 = n_2021 & n_2014; assign O[0] = n_1297; assign O[1] = n_102; assign O[2] = n_6; assign O[3] = n_16; assign O[4] = n_10; assign O[5] = n_58; assign O[6] = n_103; assign O[7] = n_60; assign O[8] = n_34; assign O[9] = n_12; assign O[10] = n_6; assign O[11] = n_1280; assign O[12] = n_2021; assign O[13] = n_20; assign O[14] = n_30; assign O[15] = n_2020; assign O[16] = n_2; assign O[17] = n_28; assign O[18] = n_22; assign O[19] = n_80; assign O[20] = n_2020; assign O[21] = n_2024; assign O[22] = n_2031; assign O[23] = n_2036; endmodule