Language ISAC and software tools

Our project is based on several former projects that were used for microprocessor design in the past. However, they are difficult to apply due to the invention of new microprocessors architectures [Moona 2000] today.

The goal of our project is the creation and especially the implementation of a language (the language name is ISAC [Hruška 2004]), which is used for description of microprocessor architecture. For good applicability of the language, it is necessary to create a development environment, which provides development of both software tools and simultaneously of microprocessor hardware. Due to the concurrent work on hardware and software (hardware/software co-design), the total time of the development will be reduced and the developmental cycle will be shortened.

Some supporting software tools are necessary during the development of microprocessor software. The development of these software tools is very time-consuming, and it requires experts at each design stage. There is usually one development team for each tool. Then the integration of created tools is difficult due to the separated development. It's clear, that the development of microprocessors proceeds in many iterations. At every case, it is necessary to change created software tools, which contain more errors. Using mixed architecture description languages solves the problem of a wrong integration of software tools. The ISAC language belongs into this category.

Our project consists of several parts. A basic research in this area is running now, and the project comes to more intensive phase, which leads to practicable results.

The project is concentrated on

  • the design of typical constructions of the description language,
  • the implementation of the software tools
    • retargetable compiler and decompiler C,
    • universal assembler and disassembler,
    • linker,
    • universal instruction-accurate and cycle-accurate simulator of microprocessors,
    • development environment for microprocessor and application design with support of multiprocessor SoC simulation,
    • hardware generator of synthesizable representation of the microprocessor.

Goals of the project

  1. Fundamental modification of an existing architecture description languages for the purpose of increasing their modeling skills,
  2. using of the new practices of formal languages and models for the purpose of model simplification (Two-Way Deterministic Translation [Lukáš 2005], Two-Way Coupled Finite Automaton [Lukáš 2007], Event Finite Automaton [Masařík 2008]),
  3. focus on description of transformation of microprocessor's model between different languages (UML [Masařík 2006], VHDL [Masařík 2007]),
  4. and finally, creation of synthesizable hardware model of microprocessor, which is used in the industrial production of the microprocessor.