Automated Analysis and Verification Research Group - VeriFIT
Publications| 2012 | Dudka Kamil, Müller Petr, Peringer Petr, Vojnar Tomáš: Predator: A Verification Tool for Programs with Dynamic Linked Data Structures, In: Lecture Notes in Computer Science, Vol. 2012, No. 7214, DE, p. 544-547, ISSN 0302-9743 |
| | Dudka Kamil, Peringer Petr, Vojnar Tomáš: An Easy to Use Infrastructure for Building Static Analysis Tools, In: Lecture Notes in Computer Science, Vol. 2012, No. 6927, DE, p. 527-534, ISSN 0302-9743 |
| | Fiedor Jan, Hrubá Vendula, Křena Bohuslav, Vojnar Tomáš: DA-BMC: A Tool Chain Combining Dynamic Analysis and Bounded Model Checking, In: Lecture Notes in Computer Science, Vol. 2012, No. 7186, DE, p. 5, ISSN 0302-9743 |
| | Fiedor Jan, Křena Bohuslav, Letko Zdeněk, Vojnar Tomáš: A Uniform Classification of Common Concurrency Errors, In: Lecture Notes in Computer Science, Vol. 2012, No. 6927, DE, p. 519-526, ISSN 0302-9743 |
| | Křena Bohuslav, Letko Zdeněk, Vojnar Tomáš: Coverage Metrics for Saturation-based and Search-based Testing of Concurrent Software, In: Lecture Notes in Computer Science, Vol. 2012, No. 7186, DE, p. 177-192, ISSN 0302-9743 |
| | Lengál Ondřej, Šimáček Jiří, Vojnar Tomáš: VATA: A Library for Efficient Manipulation of Non-Deterministic Tree Automata, In: Lecture Notes in Computer Science, Vol. 2012, No. 7214, DE, p. 79-94, ISSN 0302-9743 |
| | Letko Zdeněk, Vojnar Tomáš, Křena Bohuslav: Influence of Noise Injection Heuristics on Concurrency Coverage, In: Lecture Notes in Computer Science, Vol. 2012, No. 7119, DE, p. 123-131, ISSN 0302-9743 |
| 2011 | Abdulla Parosh A., Cederberg Jonathan, Vojnar Tomáš: Monotonic Abstraction for Programs with Multiply-Linked Structures, In: Lecture Notes in Computer Science, Vol. 2011, No. 6945, DE, p. 125-138, ISSN 0302-9743 |
| | Abdulla Parosh A., Chen Yu-Fang, Clemente Lorenzo, Holík Lukáš, Hong Chih-Duo, Mayr Richard, Vojnar Tomáš: Advanced Ramsey-based Büchi Automata Inclusion Testing, FIT-TR-2011-03, Brno, CZ, FIT VUT, 2011, p. 45 |
| | Abdulla Parosh A., Chen Yu-Fang, Clemente Lorenzo, Holík Lukáš, Hong Chih-Duo, Mayr Richard, Vojnar Tomáš: Advanced Ramsey-based Büchi Automata Inclusion Testing, In: Lecture Notes in Computer Science, Vol. 2011, No. 6901, DE, p. 187-202, ISSN 0302-9743 |
| | Bouajjani Ahmed, Bozga Marius, Habermehl Peter, Iosif Radu, Moro Pierre, Vojnar Tomáš: Programs with Lists are Counter Automata, In: Formal Methods in System Design, Vol. 38, No. 2, 2011, Berlin, DE, p. 158-192, ISSN 0925-9856 |
| | Češka Milan, Fiedor Jan, Gach Marek: A Novel Approach to Modechart Verification of Real-Time systems, In: Proceedings of the 13th International Conference on Computer Aided Systems Theory, Universidad de Las Palmas de Canaria, ES, IUCTC, 2011, p. 338-339, ISBN 978-84-693-9560-8 |
| | Dudka Kamil, Peringer Petr, Vojnar Tomáš: An Easy to Use Infrastructure for Building Static Analysis Tools, In: Proceedings of the 13th International Conference on Computer Aided Systems Theory, Universidad de Las Palmas de Canaria, ES, IUCTC, 2011, p. 328-329, ISBN 978-84-693-9560-8 |
| | Dudka Kamil, Peringer Petr, Vojnar Tomáš: Predator: A Practical Tool for Checking Manipulation of Dynamic Data Structures Using Separation Logic, In: Lecture Notes in Computer Science, Vol. 2011, No. 6806, DE, p. 372-378, ISSN 0302-9743 |
| | Dudka Kamil, Peringer Petr, Vojnar Tomáš: Predator: A Practical Tool for Checking Manipulation of Dynamic Data Structures Using Separation Logic, FIT-TR-2011-02, Brno, CZ, FIT VUT, 2011, p. 23 |
| | Fiedor Jan, Hrubá Vendula, Křena Bohuslav, Vojnar Tomáš: DA-BMC: A Tool Chain Combining Dynamic Analysis and Bounded Model Checking, FIT-TR-2011-06, Brno, CZ, FIT VUT, 2011, p. 9 |
| | Fiedor Jan, Křena Bohuslav, Letko Zdeněk, Vojnar Tomáš: A Uniform Classification of Common Concurrency Errors, In: Proceedings of the 13th International Conference on Computer Aided Systems Theory, Universidad de Las Palmas de Canaria, ES, IUCTC, 2011, p. 326-327, ISBN 978-84-693-9560-8 |
| | Habermehl Peter, Holík Lukáš, Rogalewicz Adam, Šimáček Jiří, Vojnar Tomáš: Forest Automata for Verification of Heap Manipulation, In: Lecture Notes in Computer Science, Vol. 2011, No. 6806, DE, p. 424-440, ISSN 0302-9743 |
| | Habermehl Peter, Holík Lukáš, Rogalewicz Adam, Šimáček Jiří, Vojnar Tomáš: Forest Automata for Verification of Heap Manipulation, FIT-TR-2011-01, Brno, CZ, FIT VUT, 2011, p. 30 |
| | Holík Lukáš, Lengál Ondřej, Šimáček Jiří, Vojnar Tomáš: Efficient Inclusion Checking on Explicit and Semi-Symbolic Tree Automata, In: Lecture Notes in Computer Science, Vol. 2011, No. 6996, DE, p. 243-258, ISSN 0302-9743 |
| | Holík Lukáš, Lengál Ondřej, Šimáček Jiří, Vojnar Tomáš: Efficient Inclusion Checking on Explicit and Semi-Symbolic Tree Automata, FIT-TR-2011-04, Brno, CZ, FIT VUT, 2011, p. 22 |
| | Holík Lukáš: Simulations and Antichains for Efficient Handling of Finite Automata, Brno, CZ, UITS FIT VUT, 2011, p. 128 |
| | Šimková Marcela, Lengál Ondřej, Kajan Michal: HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware, FIT-TR-2011-05, Brno, CZ, FIT VUT, 2011, p. 16 |
| 2010 | Abdulla Parosh A., Clemente Lorenzo, Holík Lukáš, Hong Chih-Duo, Chen Yu-Fang, Mayr Richard, Vojnar Tomáš: Simulation Subsumption in Ramsey-based Büchi Automata Universality and Inclusion Testing, FIT-TR-2010-02, Brno, CZ, FIT VUT, 2010, p. 30 |
| | Abdulla Parosh A., Clemente Lorenzo, Holík Lukáš, Hong Chih-Duo, Chen Yu-Fang, Mayr Richard, Vojnar Tomáš: Simulation Subsumption in Ramsey-Based Büchi Automata Universality and Inclusion Testing, In: Computer Aided Verification, Berlín, DE, Springer, 2010, p. 132-147, ISBN 978-3-642-14294-9 |
| | Abdulla Parosh A., Holík Lukáš, Chen Yu-Fang, Mayr Richard, Vojnar Tomáš: When Simulation Meets Antichains (On Checking Language Inclusion of Nondeterministic Finite (Tree) Automata), FIT-TR-2010-01, Brno, CZ, FIT VUT, 2010, p. 22 |
| | Abdulla Parosh A., Holík Lukáš, Chen Yu-Fang, Mayr Richard, Vojnar Tomáš: When Simulation Meets Antichains (On Checking Language Inclusion of Nondeterministic Finite (Tree) Automata), In: Tools and Algorithms for the Construction and Analysis of Systems, Berlín, DE, Springer, 2010, p. 158-174, ISBN 978-3-642-12001-5 |
| | Bozga Marius, Iosif Radu, Konečný Filip: Fast Acceleration of Ultimately Periodic Relations, In: Computer Aided Verification, Berlin, DE, Springer, 2010, p. 227-242, ISBN 978-3-642-14294-9 |
| | Bozga Marius, Iosif Radu, Konečný Filip: Fast Acceleration of Ultimately Periodic Relations, TR-2010-3, Grenoble, FR, VERIMAG, 2010, p. 24 |
| | Fiedor Jan, Křena Bohuslav, Letko Zdeněk, Vojnar Tomáš: A Uniform Classification of Common Concurrency Errors, FIT-TR-2010-03, Brno, CZ, 2010, p. 24 |
| | Habermehl Peter, Iosif Radu, Vojnar Tomáš: Automata-based Verification of Programs with Tree Updates, In: Acta Informatica, Vol. 47, No. 1, 2010, DE, p. 1-31, ISSN 0001-5903 |
| | Holík Lukáš, Šimáček Jiří: Optimizing an LTS-Simulation Algorithm, In: Computing and Informatics, Vol. 2010, No. 7, Bratislava, SK, p. 1337-1348, ISSN 1335-9150 |
| | Holík Lukáš, Vojnar Tomáš: Simulations and Aintichains for Efficient Handling of Tree Automata, Brno, CZ, FIT VUT, 2010, p. 150, ISBN 978-80-214-4217-7 |
| | Křena Bohuslav, Letko Zdeněk, Ur Shmuel, Vojnar Tomáš: A Platform for Search-Based Testing of Concurrent Software, In: PADTAD '10, Trento, IT, ACM, 2010, p. 11, ISBN 978-1-60558-823-0 |
| | Křena Bohuslav, Letko Zdeněk, Vojnar Tomáš, Ur Shmuel: A Platform for Search-Based Testing of Concurrent Software, 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2010, p. 1, ISBN 978-80-87342-10-7 |
| | Letko Zdeněk: Sophisticated Testing of Concurrent Programs, In: SSBSE '10, Benevento, IT, IEEE, 2010, p. 36-40, ISBN 978-0-7695-4195-2 |
| | Procházka Boris, Vojnar Tomáš, Drahanský Martin: Hijacking the Linux Kernel, In: MEMICS 2010 - Sixth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, Brno, CZ, MUNI, 2010, p. 143-150, ISBN 978-80-87342-10-7 |
| | Procházka Boris: An Attack on the Linux System Call, In: Proceedings of the 16th Conference STUDENT EEICT 2010, Brno, CZ, FEKT VUT, 2010, p. 130-132, ISBN 978-80-214-4078-4 |
| | Smrčka Aleš, Vojnar Tomáš: Verification of Asynchronous and Parametrized Hardware Designs, Brno, CZ, FIT VUT, 2010, p. 115, ISBN 978-80-214-4214-6 |
| | Smrčka Aleš: Verification of Asynchronous and Parametrized Hardware Designs, Brno, CZ, UITS FIT VUT, 2010, p. 124 |
| | Smrčka Aleš: Verification of Asynchronous and Parametrized Hardware Designs, In: Information Sciences and Technologies Bulletin of the ACM Slovakia, Vol. 2, No. 2, 2010, Bratislava, SK, p. 60-69, ISSN 1338-1237 |
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Faculty of Information Technology
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