Automated Analysis and Verification Research Group - VeriFIT

Team members

Češka Milan, prof. RNDr., CSc., UITS FIT VUT
	Formal Languages Theory Formal Specifications Petri Nets Theory System Modelling and Simulation
Dudka Kamil, Ing., UITS FIT VUT
Fiedor Jan, Ing., UITS FIT VUT
Holík Lukáš, Mgr., UITS FIT VUT
Hrubá Vendula, Ing., UITS FIT VUT
Charvát Lukáš, Ing., UITS FIT VUT
Konečný Filip, Ing., UITS FIT VUT
Křena Bohuslav, Ing., Ph.D., UITS FIT VUT
	Formal Analysis and Verification
Lengál Ondřej, Ing., UITS FIT VUT
Letko Zdeněk, Ing., UITS FIT VUT
	Operating systems, Java. Multithreading - programming, analysis, testing and healing.
Müller Petr, Ing., UITS FIT VUT
	formal verification operating systems programming languages quality assurance testing automation
Peringer Petr, Dr. Ing., UITS FIT VUT
	Modelling and Simulation Program Verification (symbolic execution, separation logic) Object-oriented programming, Design patterns C and C++ programming languages
Rogalewicz Adam, Mgr., Ph.D., UITS FIT VUT
Smrčka Aleš, Ing., Ph.D., UITS FIT VUT
	Formal analysis and verification Software testing Modelling, simulation, and verification of hardware designs
Šimáček Jiří, Ing., UITS FIT VUT
Vojnar Tomáš, prof. Ing., Ph.D., UITS FIT VUT