intMAN  version 0.2_20130422
intman_design_top.vhd
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1 -------------------------------------------------------
2 --! @file
3 --! @brief Top design of the intMAN hardware
4 --! @author Josef Strnadel, Brno University of Technology, Faculty of Information Technology
5 --! @email strnadel@fit.vutbr.cz
6 --! @date 2013-04-17
7 -------------------------------------------------------
8 
9 library IEEE;
10 use IEEE.STD_LOGIC_1164.ALL;
11 use IEEE.NUMERIC_STD.ALL;
12 use work.intMAN_package.all;
13 
14 --
15 --
16 --
17 --! intMAN unit entity (interface)
18 --
19 entity intMAN_design is
20  Port(
21  MON_INT : in STD_LOGIC; --! line to monitor whether the RT system is operating at the ISR (interrupt service routine) level
22  MON_TICK : in STD_LOGIC; --! line to monitor whether the RT system is servicing the OS (operating system) time tick
23  MON_CTX : in STD_LOGIC; --! line to monitor whether the RT system is performing a task-level context-switch
24  MON_PRI : in STD_LOGIC_VECTOR(t_pri_width_range); --! line to monitor the priority of a task running in the RT system
25  MON_SLACK : in STD_LOGIC; --! line to monitor whether there is slack time in the RT schedule
26  INT_ACK : in STD_LOGIC; --! line to acknowledge an INT service
27  INT_OUT : out STD_LOGIC_VECTOR(t_int_range); --! line to forward pending interrupt requests to the RT system
28  INT_IN : in STD_LOGIC_VECTOR(t_int_range); --! line to detect interrupt requests willing to stimulate the RT system
29  IPRI_LD : in STD_LOGIC; --! line to enable update of an interrupt configuration
30  IPRI_LD_ADDR : in STD_LOGIC_VECTOR(t_int_width_range); --! line to address the interrupt configuration of which is going to be updated
31  IPRI_LD_DATA : in STD_LOGIC_VECTOR(t_pri_width_range); --! line to adjust data going to be written into the configuration
32  CLK_1M : in STD_LOGIC; --! clock signal line
33  RST : in STD_LOGIC); --! reset signal line
34 end intMAN_design;
35 
36 --
37 --
38 --
39 --! intMAN unit architecture (inner structure)
40 --
41 architecture arch of intMAN_design is
42 
43  --! interrupt detect/buffer/config/forward for the intMAN hardware
44  component int_buf_in
45  port
46  (
47  reset : in STD_LOGIC; --! async reset
48  level : in t_intlevel_cfg; --! level-sensitivity select: log.0 (00), log. 1 (01), no (10, 11)
49  edge : in t_intedge_cfg; --! edge-sensitivity select: rising (01), falling (10), both (11), no (00)
50  clk : in STD_LOGIC; --! clock
51  int_in : in STD_LOGIC; --! incomming interrupt line
52  int_rdy : out STD_LOGIC; --! line to signalize there is a ready/pending interrupt
53  int_cnt : out t_intpend_cnt; --! number of ready/pending interrupts
54  int_pri_load : in STD_LOGIC; --! priority update enable/disable
55  int_pri_new : in STD_LOGIC_VECTOR(t_pri_width_range); --! new interrupt priority
56  int_pri : out STD_LOGIC_VECTOR(t_pri_width_range); --! interrupt priority storage
57  int_sel : in STD_LOGIC; --! interrupt forward logic enable
58  int_out : out STD_LOGIC --! line to forward the interrupt
59  );
60  end component;
61 
62  --! interrupt address unit for the intMAN hardware
63  component ipri_update_dmx
64  port
65  (
66  sel : in std_logic; --! unit enable
67  int_addr : in STD_LOGIC_VECTOR(t_int_width_range); --! selected interrupt address
68  ipri_load_sel : out STD_LOGIC_VECTOR(t_int_range) --! address dmx output with no more than one interrupt selected
69  );
70  end component;
71 
72  --! highest-priority pending interrupt selector for the intMAN hardware
73  component ipri_highest
74  port
75  (
76  IPRI_ARR : in t_intpri_arr; --! interrupt priorities
77  IPRI_HIGH: out STD_LOGIC_VECTOR(t_pri_width_range); --! the highest pending-interrupt priority
78  IPRI_ADEC: out STD_LOGIC_VECTOR(t_int_range) --! address dmx output with the highest-priority interrupt selected
79  );
80  end component;
81 
82  --! priority-condition check for the intMAN hardware
83  component c_prio
84  port (
85  monpri : in STD_LOGIC_VECTOR(t_pri_width_range); --! priority of the running task (being monitored)
86  hstipri : in STD_LOGIC_VECTOR(t_pri_width_range); --! the highest pending-interrupt priority
87  valid : out STD_LOGIC --! priority-condition result
88  );
89  end component;
90 
91  --! slack-condition check for the intMAN hardware
92  component c_slack
93  port (
94  monpri : in STD_LOGIC_VECTOR(t_pri_width_range); --! priority of the running task (being monitored)
95  monslack : in STD_LOGIC; --! slack signal (being monitored)
96  valid : out STD_LOGIC --! slack-condition result
97  );
98  end component;
99 
100 --
101 --
102 --
103 -- inner signals
104 --
105 
106 --! priority config update enable (signal)
107 signal SIG_IPRILOAD_SEL : STD_LOGIC_VECTOR(t_int_range);
108 
109 --! interrupt service start (signal)
110 signal SIG_ISERV : STD_LOGIC_VECTOR(t_int_range);
111 
112 --! pending interrupt count (signal)
114 
115 --! interrupt ready (signal)
117 
118 --! interrupt config storage (signal)
120 
121 --! interrupt config bus (signal)
123 
124 --! interrupt priorities (signal)
126 
127 --! the highest pending-interrupt priority (signal)
128 signal SIG_IPRIHVAL : STD_LOGIC_VECTOR(t_pri_width_range);
129 
130 --! address dmx output with the highest-priority interrupt selected (signal)
131 signal SIG_INTSEL : STD_LOGIC_VECTOR(t_int_range);
132 
133 --! priority-condition result (signal)
134 signal SIG_IPRICOND_VALID : STD_LOGIC;
135 
136 --! slack-condition result (signal)
137 signal SIG_SLACKCOND_VALID : STD_LOGIC;
138 
139 
140 
141 
142 begin
143  SIG_ISERV <= (OTHERS => '0');
144 
145  --! interrupt config storage unit init
146  p_icfg: process(RST) is
147  begin
148  if(RST='1') then
149  SIG_ICFG_MEM <= C_INTCFG; -- after-reset init
150  end if;
151  end process p_icfg;
152 
154 
155  --
156  --
157  --
158  -- port map section
159  --
160 
161  --! interrupt config selector unit (port map)
163  port map
164  (
165  sel => IPRI_LD,
168  );
169 
170  --! interrupt detect/buffer/config/forward unit (port map)
171  GEN_IBUF : for I in t_int_range generate
173  port map
174  (
175  reset => RST,
176  level => SIG_ICFG (I).level,
177  edge => SIG_ICFG(I).edge,
178  clk => CLK_1M,
179  int_in => INT_IN(I),
180  int_rdy => SIG_IRDY(I),
181  int_cnt => SIG_ICNT(I),
184  int_pri => SIG_IPRIARR(I),
186  int_out => INT_OUT(I)
187  );
188  end generate;
189 
190  --! highest-priority pending interrupt unit (port map)
192  port map
193  (
194  IPRI_ARR => SIG_IPRIARR,
197  );
198 
199  --! priority condition check unit (port map)
200  CPRI : c_prio
201  port map
202  (
203  monpri => MON_PRI ,
206  );
207 
208  --! priority condition check unit (port map)
209  CSLACK: c_slack
210  port map
211  (
212  monpri => MON_PRI ,
213  monslack => MON_SLACK ,
215  );
216 end arch;
© 2013 Josef Strnadel (email, web), Faculty of Information Technology, Brno University of Technology (web)