Tools for split RTL circuit into Testable blocks

Authors:Herrman Tomáš, Kotásek Zdeněk
Type:software
Created:2007
Licence:required - no fee
Files: 
+Type Name Title Size Last modified
iconcircuits.zipCircuits for testing1,74 MB2008-08-18 11:36:21
iconTB.ZIPTools for split RTL circuit into Testable blocks1,01 MB2008-04-01 15:13:53
^ Select all
With selected:
Keywords:RTL, testability analysis, formal model, scan chain design, Testable block
Description:
Developed tools make possible to split circuit written in formal model that was developed on DSC into Testable blocks and design scan chain. Outputs of tools are individual Testable blocks written in verilog.
Location:
http://www.fit.vutbr.cz/research/prod/index.php?id=57&notitle=1
Research groups:
Departments:
Licence terms:
This product is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version, see http://www.fsf.org/licensing/licenses/gpl.html

Your IPv4 address: 54.81.108.205
Switch to IPv6 connection

DNSSEC [dnssec]