Set of tools for RTL circuits testability analysis

Authors:Škarvada Jaroslav, Kotásek Zdeněk
Licence:required - no fee
Keywords:RTL, testability analysis, I-paths search, formal model, scan chain design
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Developed tools can be used for automatic transformation of digital circuit design written in structural VHDL to formal model that was developed on DCS. It is possible to use them for transparent data paths (I-paths) search, testability analysis, scan chain design. Custom cell libraries can be used.
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This product is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version, see

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