Conference paper

ČEKAN Ondřej, PÁNEK Richard and KOTÁSEK Zdeněk. Input and Output Generation for the Verification of ALU: a Use Case. In: Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018, pp. 331-336. ISBN 978-1-5386-5709-6.
Publication language:english
Original title:Input and Output Generation for the Verification of ALU: a Use Case
Title (cs):Generování vstupů a výstupů pro verifikaci ALU
Pages:331-336
Proceedings:Proceedings of IEEE East-West Design & Test Symposium
Conference:16th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM
Place:Kazan, RU
Year:2018
ISBN:978-1-5386-5709-6
DOI:10.1109/EWDTS.2018.8524641
Publisher:IEEE Computer Society
Keywords
Stimuli generation, arithmetic logic unit, probabilistic constrained grammar, functional verification
Annotation
The paper presents the approach to universal stimuli generation for an arithmetic-logic unit (ALU). It is not focused only on input data generation, but it is possible to generate also expected output in one stimulus. The process of generation is based on a probabilistic constrained grammar which is designed to universally describe stimuli for various circuits. This grammar is processed by our framework. The experiment in functional verification, which shows the quality of generated stimuli, is also presented.
BibTeX:
@INPROCEEDINGS{
   author = {Ond{\v{r}}ej {\v{C}}ekan and Richard P{\'{a}}nek
	and Zden{\v{e}}k Kot{\'{a}}sek},
   title = {Input and Output Generation for the Verification
	of ALU: a Use Case},
   pages = {331--336},
   booktitle = {Proceedings of IEEE East-West Design \& Test Symposium},
   year = 2018,
   location = {Kazan, RU},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-5386-5709-6},
   doi = {10.1109/EWDTS.2018.8524641},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=11833}
}

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