Papers

Puš, V., Kajan, M., Kořenek, J.: Hardware Architecture for Packet Classification with Prefix Coloring, In: IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011, Cottbus, DE, IEEE CS, 2011, p. 231-236, ISBN 978-1-4244-9753-9

Publication language:

english

Original title:

Hardware Architecture for Packet Classification with Prefix Coloring

Title (cs):

Hadrwarová architektura pro klasifikaci paketů s barvením prefixů

Pages:

231-236

Proceedings:

IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011

Conference:

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2011

Place:

Cottbus, DE

Year:

2011

ISBN:

978-1-4244-9753-9

Publisher:

IEEE Computer Society

Files:

Keywords

FPGA, SRAM, hardware, parallelism, classification

Annotation

Packet classification is a widely used operation in network security
devices. As network speeds are increasing, the demand for hardware
acceleration of packet classification in FPGAs or ASICs is growing.
Nowadays algorithms implemented in hardware can achieve multigigabit
speeds, but suffer with great memory overhead. We propose a new algorithm
and hardware architecture which reduces memory requirements of
decomposition based methods for packet classification. The algorithm uses
prefix coloring to reduce large amount of Cartesian product rules at the
cost of an additional pipelined processing and a few bits added into
results of the longest prefix match operation. The proposed hardware
architecture is designed as a processing pipeline with the throughput of
266 million packets per second using commodity FPGA and one external
memory. The greatest strength of the algorithm is the constant time
complexity of the search operation, which makes the solution resistant to
various classes of network security attacks.

BibTeX:

@INPROCEEDINGS{
   author = {Viktor Puš and Michal Kajan and Jan Kořenek},
   title = {Hardware Architecture for Packet Classification with Prefix
	Coloring},
   pages = {231--236},
   booktitle = {IEEE Design and Diagnostics of Electronic Circuits and
	Systems DDECS'2011},
   year = {2011},
   location = {Cottbus, DE},
   publisher = {IEEE Computer Society},
   ISBN = {978-1-4244-9753-9},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=9564}
}

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