Článek v časopise

STRAKA Martin, KAŠTIL Jan, KOTÁSEK Zdeněk a MIČULKA Lukáš. Fault Tolerant System Design and SEU Injection Based Testing. Microprocessors and Microsystems. Amsterdam: Elsevier Science, 2013, roč. 2013, č. 37, s. 155-173. ISSN 0141-9331.
Jazyk publikace:angličtina
Název publikace:Fault Tolerant System Design and SEU Injection Based Testing
Název (cs):Návrh systémů odolných proti poruchám a testování pomocí SEU injekce
Strany:155-173
Kniha:Microprocessors and Microsystems Journal SI: Digital System Safety and Security
Místo vydání:NL
Rok:2013
Časopis:Microprocessors and Microsystems, roč. 2013, č. 37, Amsterdam, NL
ISSN:0141-9331
Soubory: 
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Klíčová slova

fault tolerant system, FPGA, partial reconfiguration, controller, on-line checker, duplex, TMR, SEU, simulation, framework, fault injection

Anotace
Příspěvek prezentuje ucelenou metodiku pro návrh systémů odolných proti poruchám do obvodů FPGA, které využívají jako mechanizmus opravy částečnou dynamickou rekonfiguraci. Jsou popsány některé techniky a principy v této oblasti. Následně je popsána metodika pro konstrukci hlídacích obvodů, jsou prezentovány nové architektury odolné proti poruchám a referenční struktura takového systému. Pro řízení opravného mechanizmu, řadič rekonfigurace byl vyvinut a implementován. Bylo provedeno několik experimentů s injekcí SEU poruch do konkrétních architektur za pomoci vyvinutého SEU simulačního frameworku.
Abstrakt

The methodology for design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into SRAM-based FPGA. The methodology includes detection and localization of a faulty module in the system and its repair and bringing the system back to the state in which it operates correctly. The automatic repair process of a faulty module is implemented by a partial dynamic reconfiguration driven by a generic controller inside FPGA. The presented methodology was verified on the ML506 development board with Virtex5 FPGA for different types of RTL components. Fault tolerant systems developed by the presented methodology were tested by means of the newly developed SEU simulation framework. The framework is based on the SEU simulation through the JTAG interface and allows us to select the region of the FPGA where the SEU is placed. The simulator does not require any changes in the tested design and is fully independent of the functions in the FPGA. The external SEU generator into FPGA is implemented and its function is verified on an evaluation board ML506 for several types of fault tolerant architectures. The experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.

BibTeX:
@ARTICLE{
   author = {Martin Straka and Jan Ka{\v{s}}til and
	Zden{\v{e}}k Kot{\'{a}}sek and Luk{\'{a}}{\v{s}}
	Mi{\v{c}}ulka},
   title = {Fault Tolerant System Design and SEU Injection
	Based Testing},
   pages = {155--173},
   booktitle = {Microprocessors and Microsystems Journal SI: Digital System
	Safety and Security},
   journal = {Microprocessors and Microsystems},
   volume = {2013},
   number = {37},
   year = {2013},
   ISSN = {0141-9331},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.cs.iso-8859-2?id=9902}
}

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