Conference paper

ZACHARIÁŠOVÁ Marcela, KAŠTIL Jan and KOTÁSEK Zdeněk. Verification of Fault-tolerant methodologies for FPGA Systems. In: The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12). Annecy: Politecnico di Milano, 2012, pp. 55-58.
Publication language:english
Original title:Verification of Fault-tolerant Methodologies for FPGA Systems
Title (cs):Verifikace systémů odolných vůči poruchám pro FPGA systémy
Pages:55-58
Proceedings:The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)
Conference:MEDIAN
Place:Annecy, FR
Year:2012
Publisher:Politecnico di Milano
Keywords
fault-tolerant, FPGA, partial dynamic reconfiguration
Annotation
The aim of this paper is to fi nd a way how to utilize and compare diff erent FT methodologies we have been working with during the last few years as well as those which are new in the FT fi eld. Moreover, we present a platform for testing di erent FT methodologies implemented in an FPGA. The testing is based on the software-based injection of an SEU into the selected region of the FPGA from a PC through the JTAG interface. After fault injection into a non-speci c place in the FPGA it is necessary to explore the whole state space using input test vectors.
BibTeX:
@INPROCEEDINGS{
   author = {Marcela Zachari{\'{a}}{\v{s}}ov{\'{a}} and Jan Ka{\v{s}}til
	and Zden{\v{e}}k Kot{\'{a}}sek},
   title = {Verification of Fault-tolerant Methodologies for FPGA
	Systems},
   pages = {55--58},
   booktitle = {The First Workshop on Manufacturable and Dependable
	Multicore Architectures at Nanoscale (MEDIAN'12)},
   year = {2012},
   location = {Annecy, FR},
   publisher = {Politecnico di Milano},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en.iso-8859-2?id=10086}
}

Your IPv4 address: 54.81.45.122
Switch to IPv6 connection

DNSSEC [dnssec]