Conference paper

STRAKA Martin, KAŠTIL Jan and KOTÁSEK Zdeněk. FPGA-based Fault Tolerant Architectures and Their Dependability Analysis. In: MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Faculty of Informatics MU, 2012, pp. 1-1.
Publication language:english
Original title:FPGA-based Fault Tolerant Architectures and Their Dependability Analysis
Title (cs):Architektury odolné proti poruchám a jejich spolehlivostní analýza
Pages:1-1
Proceedings:MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Conference:MEMICS'12 -- 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
Place:Brno, CZ
Year:2012
Publisher:Faculty of Informatics MU
Keywords
reliability, dependability, FPGA
Annotation
In this presentation, a dependability analysis of fault tolerant architectures implemented into the SRAM-based FPGA with reconfiguration controller are presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of PDR as a recovery mechanism from a fault occurrence caused by Single Event Upsets (SEU). Architectures are tested by injecting soft errors into partial bitstreams in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, Markov dependability models for fault tolerant architectures are created and it is demonstrated how the reliability and availability parameters can be derived from this model for different configurations of architectures. The presentation will be based mainly on the paper, which was presented at the 15th EUROMICRO DSD 2012.

Abstract
In this presentation, a dependability analysis of fault tolerant architectures implemented into the SRAM-based FPGA with reconfiguration controller are presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of PDR as a recovery mechanism from a fault occurrence caused by Single Event Upsets (SEU). Architectures are tested by injecting soft errors into partial bitstreams in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, Markov dependability models for fault tolerant architectures are created and it is demonstrated how the reliability and availability parameters can be derived from this model for different configurations of architectures. The presentation will be based mainly on the paper, which was presented at the 15th EUROMICRO DSD 2012.
BibTeX:
@INPROCEEDINGS{
   author = {Martin Straka and Jan Ka{\v{s}}til and Zden{\v{e}}k
	Kot{\'{a}}sek},
   title = {FPGA-based Fault Tolerant Architectures and Their
	Dependability Analysis},
   pages = {1--1},
   booktitle = {MEMICS'12 -- 8th Doctoral Workshop on Mathematical and
	Engineering Methods in Computer Science},
   year = {2012},
   location = {Brno, CZ},
   publisher = {Faculty of Informatics MU},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php.en.iso-8859-2?id=10166}
}

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