Publication Details

Design and Implementation of the Memory Scheduler for the FPGA - Based Router

BRYAN Luděk, MAREK Tomáš and NOVOTNÝ Martin. Design and Implementation of the Memory Scheduler for the FPGA - Based Router. In: Proc. of the Field Programmable Logic and Application 2004. Leuven: Springer Verlag, 2004, pp. 1133-1139. ISBN 3-540-22989-2.

Czech title

Design a implementace paměťového řadiče pro router na bázi FPGA

Type

conference paper

Language

english

Authors

Bryan Luděk, Ing. (DCSY FIT BUT)
Marek Tomáš, Ing. (FEE CTU)
Novotný Martin, Dr. Ing. (FEE CTU)

Keywords

FPGA, DDR SDRAM, memory, router, IPV6

Abstract

This paper deals with a design of a memory scheduler as a part of the Liberouter project.

Published

2004

Pages

1133-1139

Proceedings

Proc. of the Field Programmable Logic and Application 2004

Conference

The International Conference on Field- Programmable Logic and Applications, Antwerp, BE

ISBN

3-540-22989-2

Publisher

Springer Verlag

Place

Leuven, BE

BibTeX

@INPROCEEDINGS{FITPUB7636,
   author = "Lud\v{e}k Bryan and Tom\'{a}\v{s} Marek and Martin Novotn\'{y}",
   title = "Design and Implementation of the Memory Scheduler for the FPGA - Based Router",
   pages = "1133--1139",
   booktitle = "Proc. of the Field Programmable Logic and Application 2004",
   year = 2004,
   location = "Leuven, BE",
   publisher = "Springer Verlag",
   ISBN = "3-540-22989-2",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/7636"
}