ZACHARIÁŠOVÁ Marcela. Hardware Accelerated Functional Verification - Framework for FPGA-Accelerated Functional Verification. Saarbrucken: Lambert Academic Publishing, 2011. ISBN 978-3-8465-5913-0.
Publication language:english
Original title:Hardware Accelerated Functional Verification
Title (cs):Hardwarově akcelerovaná funkční verifikace - Prostředí pro akceleraci funkční verifikace pomocí FPGA
Place:Saarbrucken, DE
Publisher:Lambert Academic Publishing
functional verification, FPGA, acceleration, SystemVerilog
Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. This thesis introduces a design of a verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification, while retaining the possibility to run verification also in the user-friendly debugging environment of a simulator. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM) as well as assertion-based verification, making its application range quite large. According to the experiments carried out on a prototype implementation, the achieved acceleration is proportional to the number of checked transactions and the complexity of the verified system. The maximum acceleration achieved on the set of experiments was over 130 times.
   author = {Marcela Zachari{\'{a}}{\v{s}}ov{\'{a}}},
   title = {Hardware Accelerated Functional Verification},
   pages = 60,
   year = 2011,
   location = {Saarbrucken, DE},
   publisher = {Lambert Academic Publishing},
   ISBN = {978-3-8465-5913-0},
   language = {english},
   url = {}

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