Conference paper

ZACHARIÁŠOVÁ Marcela. Acceleration of Functional Verification in the Development Cycle of Hardware Systems. In: Počítačové architektury a diagnostika. Praha: Czech Technical University, 2012, pp. 73-78. ISBN 978-80-01-05106-1.
Publication language:english
Original title:Acceleration of Functional Verification in the Development Cycle of Hardware Systems
Title (cs):Využití akcelerace funkční verifikaci při vývoji hardwarových systémů
Pages:73-78
Proceedings:Počítačové architektury a diagnostika
Conference:Počítačové architektury a diagnostika 2012, PAD 2012
Place:Praha, CZ
Year:2012
ISBN:978-80-01-05106-1
Publisher:Czech Technical University
Keywords
functional verification, hardware acceleration, genetic algorithm, optimization
Annotation
Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. I introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.The second approach utilizes genetic algorithm in order to optimize and automate a technique called coverage-driven verification.
BibTeX:
@INPROCEEDINGS{
   author = {Marcela Zachari{\'{a}}{\v{s}}ov{\'{a}}},
   title = {Acceleration of Functional Verification in the Development
	Cycle of Hardware Systems},
   pages = {73--78},
   booktitle = {Po{\v{c}}{\'{i}}ta{\v{c}}ov{\'{e}} architektury a
	diagnostika},
   year = {2012},
   location = {Praha, CZ},
   publisher = {Czech Technical University},
   ISBN = {978-80-01-05106-1},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=10139}
}

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