Conference paper

PUŠ Viktor and KOŘENEK Jan. Reducing memory in high-speed packet classification. In: Proceedings of the 8th International Wireless Communications and Mobile Computing Conference. Limassol: Frederick University, 2012, pp. 437-442. ISBN 978-1-4577-1377-4.
Publication language:english
Original title:Reducing memory in high-speed packet classification
Title (cs):Redukce paměti ve vysokorychlostní klasifikaci paketů
Proceedings:Proceedings of the 8th International Wireless Communications and Mobile Computing Conference
Conference:IWCMC 2012 Wireless LANs and Wireless PANs Symposium
Place:Limassol, CY
Publisher:Frederick University
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icon01_Pus.pdfpus12130 KB2012-10-10 00:00:08
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FPGA, SRAM, hardware, parallelism, classification
Many packet classification algorithms were proposed to deal with the rapidly growing speed of computer networks. Unfortunately all of these algorithms are able to achieve high throughput only at the cost of excessively large memory and can be used only for small sets of rules. We propose new algorithm that uses four techniques to lower the memory requirements: division of rule set into subsets, removal of critical rules, prefix coloring and perfect hashing. The algorithm is designed for pipelined hardware implementation, can achieve the throughput of 266 million packets per second, which corresponds to 178 Gb/s for the shortest 64B packets, and outperforms older approaches in terms of memory requirements by 66 % in average for the rule sets available to us.
   author = {Viktor Pu{\v{s}} and Jan Ko{\v{r}}enek},
   title = {Reducing memory in high-speed packet classification},
   pages = {437--442},
   booktitle = {Proceedings of the 8th International Wireless Communications
	and Mobile Computing Conference},
   year = {2012},
   location = {Limassol, CY},
   publisher = {Frederick University},
   ISBN = {978-1-4577-1377-4},
   language = {english},
   url = {}

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