Conference paper

KEKELY Lukáš, PUŠ Viktor and KOŘENEK Jan. Low-Latency Modular Packet Header Parser for FPGA. In: ACM/IEEE Symposium on Architectures for Networking and Communications Systems. Austin: Association for Computing Machinery, 2012, pp. 77-78. ISBN 978-1-4503-1685-9.
Publication language:english
Original title:Low-Latency Modular Packet Header Parser for FPGA
Title (cs):Nízko-latentní modulární analyzátor hlaviček paketov pro FPGA
Pages:77-78
Proceedings:ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Conference:ACM/IEEE Symposium on Architectures for Networking and Communications Systems 2012
Place:Austin, US
Year:2012
ISBN:978-1-4503-1685-9
Publisher:Association for Computing Machinery
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Keywords
Packet Parsing, Latency, FPGA
Annotation
Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application. The parser is handoptimized thanks to the direct implementation in VHDL, yet the structure is very uniform and easily extensible for new protocols.
BibTeX:
@INPROCEEDINGS{
   author = {Luk{\'{a}}{\v{s}} Kekely and Viktor Pu{\v{s}} and Jan
	Ko{\v{r}}enek},
   title = {Low-Latency Modular Packet Header Parser for FPGA},
   pages = {77--78},
   booktitle = {ACM/IEEE Symposium on Architectures for Networking and
	Communications Systems},
   year = {2012},
   location = {Austin, US},
   publisher = {Association for Computing Machinery},
   ISBN = {978-1-4503-1685-9},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=10197}
}

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