Conference paper

PŘIKRYL Zdeněk. Fast Simulation of Pipeline in ASIP simulators. In: 15th International Workshop on Microprocessor Test and Verification. Austin: IEEE Computer Society, 2014, pp. 1-6. ISBN 978-0-7695-4000-9.
Publication language:english
Original title:Fast Simulation of Pipeline in ASIP Simulators
Title (cs):Rychlá simulaci linky zřetězení v simulátorech aplikačně specifických procesorů
Proceedings:15th International Workshop on Microprocessor Test and Verification
Conference:Microprocessor Test and Verification 2014
Place:Austin, US
Publisher:IEEE Computer Society
ASIP, Simulator, Pipeline
A fast and accurate simulator of the newly designed application specific instruction-set processors is essential during processor development, testing, and verification as well as for software development. Instruction-set simulators are usually used at the early stages of the design. They have good performance, but because of their low accuracy they cannot be used for a detailed pipeline or timing analysis. For this task, cycle-accurate simulators are used. They are of high accuracy since the whole microarchitecture is simulated. But at the same time, the simulation time can be significantly longer than in the case of instruction-set simulators. We present a technique which reduces the simulation time with an acceleration of pipeline simulation. Experimental results show a speed-up during simulation. Moreover, the proposed concept can also be used for hardware realization of application specific instruction-set processors.
   author = {Zden{\v{e}}k P{\v{r}}ikryl},
   title = {Fast Simulation of Pipeline in ASIP Simulators},
   pages = {1--6},
   booktitle = {15th International Workshop on Microprocessor Test and
   year = 2014,
   location = {Austin, US},
   publisher = {IEEE Computer Society},
   ISBN = {978-0-7695-4000-9},
   doi = {10.1109/MTV.2014.18},
   language = {english},
   url = {}

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