Conference paper

LOJDA Jakub and KOTÁSEK Zdeněk. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. In: Počítačové architektury & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017, pp. 59-62. ISBN 978-80-972784-0-3.
Publication language:czech
Original title:Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy
Title (en):Fault Tolerant Systems Design Automation Using High-Level Synthesis
Proceedings:Počítačové architektury & diagnostika 2017
Conference:Počítačové architektury a diagnostika 2017
Place:Smolenice, SK
Publisher:Slovak University of Technology in Bratislava
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iconPAD_2017_lojda.pdf516 KB2017-09-18 10:53:29
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Design Automation, HLS, High-Level Synthesis, CatapultC, Fault Tolerance, Fault Tolerant System
As chip-level integration grows, it is becoming a great challenge to effectively utilize provided resources, which results in research in the filed of new digital systems design methodologies. One of these methodologies is the so-called High-Level Synthesis (HLS), which is often used in combination with Field Programmable Gate Arrays (FPGAs). The general objective of our research is to find a method to incorporate Fault Tolerance (FT) design methodologies into these new techniques of FT design and to automate the process of FT systems design. First steps towards redundancy insertion and evaluation of the importance of particular operations are presented in this paper.
   author = {Jakub Lojda and Zden{\v{e}}k Kot{\'{a}}sek},
   title = {Automatizace n{\'{a}}vrhu syst{\'{e}}m{\r{u}} odoln{\'{y}}ch
	proti poruch{\'{a}}m pomoc{\'{i}}
	vysoko{\'{u}}rov{\v{n}}ov{\'{e}} synt{\'{e}}zy},
   pages = {59--62},
   booktitle = {Po{\v{c}}{\'{i}}ta{\v{c}}ov{\'{e}} architektury \&
	diagnostika 2017},
   year = {2017},
   location = {Smolenice, SK},
   publisher = {Slovak University of Technology in Bratislava},
   ISBN = {978-80-972784-0-3},
   language = {czech},
   url = {}

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