Conference paper

SEKANINA Lukáš and RŮŽIČKA Richard. Design of the Special Fast Reconfigurable Chip Using Common FPGA. In: Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000, pp. 161-168. ISBN 80-968320-3-4.
Publication language:english
Original title:Design of the Special Fast Reconfigurable Chip Using Common FPGA
Title (cs):Návrh speciálního rychle rekonfigurovatelného obvodu s využitím běžného FPGA
Pages:161-168
Proceedings:Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000
Conference:Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000
Place:Smolenice, SK
Year:2000
ISBN:80-968320-3-4
URL:http://www.fit.vutbr.cz/~sekanina/publ/ddecs00/rechip.pdf [PDF]
Keywords
reconfigurable circuits, evolvable hardware
Annotation
Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.
Abstract
BibTeX:
@INPROCEEDINGS{
   author = {Luk{\'{a}}{\v{s}} Sekanina and Richard
	R{\r{u}}{\v{z}}i{\v{c}}ka},
   title = {Design of the Special Fast Reconfigurable Chip Using Common
	FPGA},
   pages = {161--168},
   booktitle = {Proc. of Design and Diagnostics of Electronic Circuits and
	Systems - IEEE DDECS'2000},
   year = {2000},
   location = {Smolenice, SK},
   ISBN = {80-968320-3-4},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=6394}
}

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