Conference paper

KUTÁLEK Vladimír and DVOŘÁK Václav. A multi-protocol cache controller. In: IFAC Workshop on Programmable devices and systems - PDS 2003. Ostrava: VŠB - Technical University of Ostrava, 2003, pp. 220-225. ISBN 0-08-044130-0.
Publication language:english
Original title:A Multi-protocol cache controller
Title (cs):Víceprotokolový řadič paměti cache
Pages:220-225
Proceedings:IFAC Workshop on Programmable devices and systems - PDS 2003
Conference:IFAC Workshop on Programmable Devices and Systems
Place:Ostrava, CZ
Year:2003
ISBN:0-08-044130-0
Publisher:VŠB - Technical University of Ostrava
Keywords
Cache coherence protocols, Bus multiprocessor systems, Tuning characteristics.
Annotation
Bus-based shared memory multiprocessors with per-processor caches use either invalidation or update protocols to maintain cache coherence. This paper suggests mixing protocols for different data objects within a single application, depending on whatever protocol is more efficient for an access pattern to a given object. The model of a two-protocol cache coherence controller has been created in CSP-based Transim language. Each cache line is tagged not only with the state, but also with the protocol type. Two most frequent 4-state, write-back protocols are implemented: MESI (invalidation) and Dragon (update) protocol. The model will be used for experimental evaluation of the proposed controller, which could then be used for processor cores with primary caches in SoC or for secondary caches in multiprocessors with standard microprocessors.
BibTeX:
@INPROCEEDINGS{
   author = {Vladim{\'{i}}r Kut{\'{a}}lek and V{\'{a}}clav
	Dvo{\v{r}}{\'{a}}k},
   title = {A Multi-protocol cache controller},
   pages = {220--225},
   booktitle = {IFAC Workshop on Programmable devices and systems - PDS 2003},
   year = {2003},
   location = {Ostrava, CZ},
   publisher = {V{\v{S}}B - Technical University of Ostrava},
   ISBN = {0-08-044130-0},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=7122}
}

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