Conference paper

KOTÁSEK Zdeněk, TUPEC Pavel and URBIŠ Hynek. Testing PCBs Based on Boundary Scan. In: Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003, pp. 119-122. ISBN 80-7099-509-2.
Publication language:english
Original title:Testing PCBs Based on Boundary Scan
Pages:119-122
Proceedings:Proceedings of International Carpathian Control Conference
Conference:International Carpathian Control Conference
Place:Košice, SK
Year:2003
ISBN:80-7099-509-2
Publisher:The University of Technology Košice
Keywords
Boundary Scan, PCB, FPGA
Annotation
The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools.
BibTeX:
@INPROCEEDINGS{
   author = {Zden{\v{e}}k Kot{\'{a}}sek and Pavel Tupec and Hynek
	Urbi{\v{s}}},
   title = {Testing PCBs Based on Boundary Scan},
   pages = {119--122},
   booktitle = {Proceedings of International Carpathian Control Conference},
   year = {2003},
   location = {Ko{\v{s}}ice, SK},
   publisher = {The University of Technology Ko{\v{s}}ice},
   ISBN = {80-7099-509-2},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=7216}
}

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