Conference paper

RŮŽIČKA Richard. Testable Design Verification Using Petri Nets. In: Proceedings of Euromicro Symposium on Digital System Design 2003. Los Alamitos, CA: IEEE Computer Society Press, 2003, pp. 304-311. ISBN 0-7695-2003-0.
Publication language:english
Original title:Testable Design Verification Using Petri Nets
Title (cs):Verifikace testovatelného návrhu s využitím Petriho sítí
Proceedings:Proceedings of Euromicro Symposium on Digital System Design 2003
Conference:EUROMICRO Symposium on Digital System Design: Architecture, Methods and Tools
Place:Los Alamitos, CA, US
Publisher:IEEE Computer Society Press
Testability Analysis, Testability Verification, Petri Nets, I path, RTL Digital Circuits
In the paper, a method for formal verification of testable design is presented. As a input, a digital circuit structure at RT level designed using any DfT technique is assumed. Proposed method enables to verify testability of each element or a part of the circuit. Petri Net based model and common methods of Petri Net analysis are utilised. On the model, it is possible to prove, if a circuit element or a part of the circuit under test can be tested by a selected way - if paths, chosen for diagnostic data transport, are passable or not and if not, for what reason.
   author = {Richard R{\r{u}}{\v{z}}i{\v{c}}ka},
   title = {Testable Design Verification Using Petri Nets},
   pages = {304--311},
   booktitle = {Proceedings of Euromicro Symposium on Digital System Design
   year = {2003},
   location = {Los Alamitos, CA, US},
   publisher = {IEEE Computer Society Press},
   ISBN = {0-7695-2003-0},
   language = {english},
   url = {}

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