Conference paper

KOTÁSEK Zdeněk and TUPEC Pavel. New approach to the FPGA testing based on the Boundary Scan. In: Proceedings of 38th International Conference MOSIS'04. Ostrava, 2004, pp. 120-123. ISBN 80-85988-98-4.
Publication language:english
Original title:New approach to the FPGA testing based on the Boundary Scan
Title (cs):Nový přístup k testování FPGA využívající Boundary Scan
Pages:120-123
Proceedings:Proceedings of 38th International Conference MOSIS'04
Conference:MOSIS 2004 - Modelling and Simulation of Systems
Place:Ostrava, CZ
Year:2004
ISBN:80-85988-98-4
Keywords
JTAG, debugger, RT level, boundary scan
Annotation
In the paper, a method enabling to verify the functionality of an FPGA design is presented. This method is based on the formal model construction of the register transfer (RT) level digital circuit. This new approach allows FPGA designers to debug and verify their hardware being developed. A Boundary scan is used as a communication interface. As an input, a digital circuit structure at RT level designed using any DfT technique is assumed.
Abstract
FPGA testing
BibTeX:
@INPROCEEDINGS{
   author = {Zden{\v{e}}k Kot{\'{a}}sek and Pavel Tupec},
   title = {New approach to the FPGA testing based on the Boundary Scan},
   pages = {120--123},
   booktitle = {Proceedings of 38th International Conference MOSIS'04},
   year = {2004},
   location = {Ostrava, CZ},
   ISBN = {80-85988-98-4},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=7458}
}

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