Publication Details

New approach to the FPGA testing based on the Boundary Scan

KOTÁSEK Zdeněk and TUPEC Pavel. New approach to the FPGA testing based on the Boundary Scan. In: Proceedings of 38th International Conference MOSIS'04. Ostrava, 2004, pp. 120-123. ISBN 80-85988-98-4.
Czech title
Nový přístup k testování FPGA využívající Boundary Scan
Type
conference paper
Language
english
Authors
Kotásek Zdeněk, doc. Ing., CSc. (DCSY FIT BUT)
Tupec Pavel, Ing. (DCSY FIT BUT)
Keywords

JTAG, debugger, RT level, boundary scan

Abstract

In the paper, a method enabling to verify the functionality of an FPGA design is presented. This method is based on the formal model construction of the register transfer (RT) level digital circuit. This new approach allows FPGA designers to debug and verify their hardware being developed. A Boundary scan is used as a communication interface. As an input, a digital circuit structure at RT level designed using any DfT technique is assumed.

Annotation

FPGA testing

Published
2004
Pages
120-123
Proceedings
Proceedings of 38th International Conference MOSIS'04
Conference
MOSIS 2004 - Modelling and Simulation of Systems, Rožnov pod Radhoštěm, CZ
ISBN
80-85988-98-4
Place
Ostrava, CZ
BibTeX
@INPROCEEDINGS{FITPUB7458,
   author = "Zden\v{e}k Kot\'{a}sek and Pavel Tupec",
   title = "New approach to the FPGA testing based on the Boundary Scan",
   pages = "120--123",
   booktitle = "Proceedings of 38th International Conference MOSIS'04",
   year = 2004,
   location = "Ostrava, CZ",
   ISBN = "80-85988-98-4",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/7458"
}
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