Conference paper

ŠKARVADA Jaroslav. Verifikace testovatelnosti návrhu číslicového obvodu. In: Proceedings of 10th Conference and Competition Student EEICT 2004, Volume 1. Brno: Faculty of Electrical Engineering and Communication BUT, 2004, pp. 275-277. ISBN 80-214-2634-9.
Publication language:czech
Original title:Verifikace testovatelnosti návrhu číslicového obvodu
Title (en):RT level digital circuit design testability verification
Pages:275-277
Proceedings:Proceedings of 10th Conference and Competition Student EEICT 2004, Volume 1
Conference:Student EEICT 2004
Place:Brno, CZ
Year:2004
ISBN:80-214-2634-9
Publisher:Faculty of Electrical Engineering and Communication BUT
URL:http://www.feec.vutbr.cz/EEICT/2004/sbornik/02-Magisterske_projekty/09-Pocitacove_systemy/06-xskarv02.pdf [PDF]
Keywords
RT level digital circuit design testability verification, testability, I-path, I-mode, register transfer level, partial scan, C/E Petri net, conflicts and deadlocks, reachability of marking, INA
Annotation
The main goal of this work is to develop and implement software system for automatic testabilty verification of Register Transfer (RT) level Digital Circuit Design (DCD). In the implementation of the system, a C/E Petri Nets approach is used. The input to the system is formal specification of DCD and the output from the system is the decision if the DCD is testable or not.
BibTeX:
@INPROCEEDINGS{
   author = {Jaroslav {\v{S}}karvada},
   title = {Verifikace testovatelnosti n{\'{a}}vrhu
	{\v{c}}{\'{i}}slicov{\'{e}}ho obvodu},
   pages = {275--277},
   booktitle = {Proceedings of 10th Conference and Competition Student EEICT
	2004, Volume 1},
   year = {2004},
   location = {Brno, CZ},
   publisher = {Faculty of Electrical Engineering and Communication BUT},
   ISBN = {80-214-2634-9},
   language = {czech},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=7595}
}

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