Journal article

SEKANINA Lukáš and FRIEDL Štěpán. An Evolvable Combinational Unit for FPGAs. Computing and Informatics. Bratislava: Slovak Academic Press, 2004, vol. 23, no. 5, pp. 461-486. ISSN 1335-9150.
Publication language:english
Original title:An Evolvable Combinational Unit for FPGAs
Title (cs):Vyvíjející se kombinační jednotka pro FPGA
Journal:Computing and Informatics, Vol. 23, No. 5, Bratislava, SK
combinational circuit, evolutionary design, evolvable hardware, field programmable gate array
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.
   author = {Luk{\'{a}}{\v{s}} Sekanina and {\v{S}}t{\v{e}}p{\'{a}}n
   title = {An Evolvable Combinational Unit for FPGAs},
   pages = {461--486},
   journal = {Computing and Informatics},
   volume = {23},
   number = {5},
   year = {2004},
   ISSN = {1335-9150},
   language = {english},
   url = {}

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