Conference paper

MATOUŠEK Petr, SMRČKA Aleš and VOJNAR Tomáš. High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design. In: Correct Hardware Design and Verification Methods. Berlin: Springer Verlag, 2005, pp. 371-375. ISBN 978-3-540-29105-3. ISSN 0302-9743.
Publication language:english
Original title:High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design
Title (cs):Vysokoúrovňové modelování, analýza a verifikace návrhu hardware založeného na FPGA
Proceedings:Correct Hardware Design and Verification Methods
Series:Lecture Notes in Computer Science 3725/2005
Place:Berlin, DE
Journal:Lecture Notes in Computer Science, Vol. 2005, No. 3725, DE
Publisher:Springer Verlag
formal analysis and verification, timed automata, parametric analysis, FPGA, hardware, computer networks
The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too.
   author = {Petr Matou{\v{s}}ek and Ale{\v{s}} Smr{\v{c}}ka
	and Tom{\'{a}}{\v{s}} Vojnar},
   title = {High-Level Modelling, Analysis, and Verification
	on FPGA-Based Hardware Design},
   pages = {371--375},
   booktitle = {Correct Hardware Design and Verification Methods},
   series = {Lecture Notes in Computer Science 3725/2005},
   journal = {Lecture Notes in Computer Science},
   volume = 2005,
 number = 3725,
   year = 2005,
   location = {Berlin, DE},
   publisher = {Springer Verlag},
   ISBN = {978-3-540-29105-3},
   ISSN = {0302-9743},
   language = {english},
   url = {}

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