Conference paper

ŠKARVADA Jaroslav. Test Scheduling for SOC under Power Constraints. In: Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006, pp. 91-93. ISBN 1-4244-0184-4.
Publication language:english
Original title:Test Scheduling for SOC under Power Constraints
Title (cs):Plánování testu pro SOC zohledňující příkon energie
Pages:91-93
Proceedings:Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Conference:IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop
Place:Prague, CZ
Year:2006
ISBN:1-4244-0184-4
Publisher:Czech Technical University Publishing House
Keywords
test scheduling, power constraint, test application conflict graph, genetic algorithm
Annotation
The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research.
BibTeX:
@INPROCEEDINGS{
   author = {Jaroslav {\v{S}}karvada},
   title = {Test Scheduling for SOC under Power Constraints},
   pages = {91--93},
   booktitle = {Proceedings of the 2006 IEEE Workshop on Design and
	Diagnostics of Electronic Circuits and Systems},
   year = {2006},
   location = {Prague, CZ},
   publisher = {Czech Technical University Publishing House},
   ISBN = {1-4244-0184-4},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8031}
}

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