Conference paper

HERRMAN Tomáš. Formal Model of Testable Block. In: Proceedings of 12th Conference Student EEICT 2006, Volume 4. Brno: Faculty of Electrical Engineering and Communication BUT, 2006, pp. 451-455. ISBN 80-214-3163-6.
Publication language:english
Original title:Formal Model of Testable Block
Title (cs):Formální model Testovatelného bloku
Pages:451-455
Proceedings:Proceedings of 12th Conference Student EEICT 2006, Volume 4
Conference:Student EEICT 2006
Place:Brno, CZ
Year:2006
ISBN:80-214-3163-6
Publisher:Faculty of Electrical Engineering and Communication BUT
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iconherrman2.docFormal Model of Testable Block - papaer84,5 KB2006-04-27 23:04:02
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Keywords
RT level, Testable block, formal model, scan chain
Annotation
Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.
BibTeX:
@INPROCEEDINGS{
   author = {Tom{\'{a}}{\v{s}} Herrman},
   title = {Formal Model of Testable Block},
   pages = {451--455},
   booktitle = {Proceedings of 12th Conference Student EEICT 2006, Volume 4},
   year = {2006},
   location = {Brno, CZ},
   publisher = {Faculty of Electrical Engineering and Communication BUT},
   ISBN = {80-214-3163-6},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8051}
}

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