Conference paper

HERRMAN Tomáš. Testability Analysis Based on Formal Model. In: Proceedings of the Sevnth International Scientific Conference ECI 2006. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2006, pp. 243-248. ISBN 80-8073-598-0.
Publication language:english
Original title:Testability Analysis Based on Formal Model
Title (cs):Analýza testovatelnosti založená na formálním modelu
Pages:243-248
Proceedings:Proceedings of the Sevnth International Scientific Conference ECI 2006
Conference:7TH International Scientific Conference Electronic Computers and Informatics 2006
Place:Košice, SK
Year:2006
ISBN:80-8073-598-0
Publisher:Faculty of Electrical Engineering and Informatics, University of Technology Košice
Keywords
formal model, RT level, testable block, testability analysis
Annotation
Formal model of a circuit on RT level is described in this paper. The model is used to describe properties of Testable Block. It is indicated how the concept of Testable Block can be used to reduce RT level test application time by decreasing the number of register included into scan chain.
BibTeX:
@INPROCEEDINGS{
   author = {Tom{\'{a}}{\v{s}} Herrman},
   title = {Testability Analysis Based on Formal Model},
   pages = {243--248},
   booktitle = {Proceedings of the Sevnth International Scientific
	Conference ECI 2006},
   year = {2006},
   location = {Ko{\v{s}}ice, SK},
   publisher = {Faculty of Electrical Engineering and Informatics,
	University of Technology Ko{\v{s}}ice},
   ISBN = {80-8073-598-0},
   language = {english},
   url = {http://www.fit.vutbr.cz/research/view_pub.php?id=8176}
}

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